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Travelled to:
3 × France
3 × Germany
Collaborated with:
T.Hwang F.Chen K.Wang Y.Chen C.L.Liu
Talks about:
dual (3) architectur (2) crosstalk (2) synthesi (2) memori (2) logic (2) rail (2) dimension (1) uniform (1) perform (1)

Person: Yi-Yu Liu

DBLP DBLP: Liu:Yi=Yu

Contributed to:

DATE 20132013
DATE 20092009
DATE 20082008
DATE 20062006
DATE v2 20042004
DATE 20012001

Wrote 6 papers:

DATE-2013-ChenL #2d #architecture #data access #memory management
Dual-addressing memory architecture for two-dimensional memory access patterns (YHC, YYL), pp. 71–76.
DATE-2009-ChenL #design
Performance-driven dual-rail insertion for chip-level pre-fabricated design (FWC, YYL), pp. 308–311.
DATE-2008-ChenL #architecture
Wire Sizing Alternative — An Uniform Dual-rail Routing Architecture (FWC, YYL), pp. 796–799.
DATE-2006-LiuH #logic #synthesis
Crosstalk-aware domino logic synthesis (YYL, TH), pp. 1312–1317.
DATE-v2-2004-LiuWH #logic #synthesis
Crosstalk Minimization in Logic Synthesis for PLA (YYL, KHW, TH), pp. 790–795.
DATE-2001-LiuWHL #diagrams
Binary decision diagram with minimum expected path length (YYL, KHW, TH, CLL), pp. 708–712.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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