Travelled to:1 × Denmark
1 × Israel
2 × USA
Collaborated with:A.McIsaac K.Eder ∅ F.Casaubieilh M.Benjamin M.Bartley F.Pogodalla F.Rocheteau M.Belhadj J.Eggleton G.Mas C.Berthet
Talks about:processor (2) verif (2) model (2) check (2) microprocessor (1) methodolog (1) interlock (1) chameleon (1) function (1) virtual (1)
Person: Geoff Barrett
DBLP: Barrett:Geoff
Contributed to:
2002
19971996
1993Wrote 4 papers:
- DAC-2002-EderB #logic #performance #pipes and filters #verification
- Achieving maximum performance: a method for the verification of interlocked pipeline control logic (KE, GB), pp. 135–140.
- CAV-1997-BarrettM #design #model checking
- Model Checking in a Microprocessor Design Project (GB, AM), pp. 214–225.
- DAC-1996-CasaubieilhMBBPRBEMBB #functional #verification
- Functional Verification Methodology of Chameleon Processor (FC, AM, MB, MB, FP, FR, MB, JE, GM, GB, CB), pp. 421–426.
- FME-1993-Barrett #model checking
- Model Checking in Practice — The T9000 Virtual Channel Processor (GB), pp. 129–147.