Travelled to:1 × France
1 × Germany
1 × USA
Collaborated with:G.d.Pendina O.Goncalves B.Dieny L.Rolíndez S.Mir A.Bounceur C.Layer K.Jaber R.C.Sousa I.L.Prejbeanu J.Nozieres
Talks about:test (2) chip (2) implement (1) spintron (1) volatil (1) pattern (1) generat (1) analogu (1) signal (1) replac (1)
Person: Guillaume Prenat
DBLP: Prenat:Guillaume
Contributed to:
2014
20132004Wrote 3 papers:
- DATE-2014-PrenatPLGJDSPN #logic #power management
- Magnetic memories: From DRAM replacement to ultra low power logic chips (GP, GdP, CL, OG, KJ, BD, RCS, ILP, JPN), p. 1.
- DAC-2013-GoncalvesPPD
- Non-volatile FPGAs based on spintronic devices (OG, GP, GdP, BD), p. 3.
- DATE-v1-2004-RolindezMPB #generative #implementation
- A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns (LR, SM, GP, AB), pp. 706–707.