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Travelled to:
1 × France
3 × USA
Collaborated with:
C.J.Alpert P.Villarrubia R.Puri M.Cho H.Xiang D.Z.Pan N.Viswanathan G.Nam C.C.N.Chu L.N.Reddy S.Krishnaswamy C.Washburn J.Earl J.Keinert
Talks about:
placement (2) base (2) synthesi (1) quadrat (1) perform (1) network (1) histori (1) circuit (1) spread (1) migrat (1)

Person: Haoxing Ren

DBLP DBLP: Ren:Haoxing

Contributed to:

DATE 20132013
DAC 20102010
DAC 20072007
DAC 20052005

Wrote 4 papers:

DATE-2013-RenPRKWEK #performance #synthesis
Intuitive ECO synthesis for high performance circuits (HR, RP, LNR, SK, CW, JE, JK), pp. 1002–1007.
DAC-2010-ChoRXP #network #using
History-based VLSI legalization using network flow (MC, HR, HX, RP), pp. 286–291.
DAC-2007-ViswanathanNAVRC #named #polynomial
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization (NV, GJN, CJA, PV, HR, CCNC), pp. 453–458.
DAC-2005-RenPAV #migration
Diffusion-based placement migration (HR, DZP, CJA, PV), pp. 515–520.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.