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Travelled to:
1 × France
1 × Germany
12 × USA
Collaborated with:
J.Gu M.Cho D.Z.Pan L.Stok H.Xiang C.Chuang W.H.Joyner H.Ren S.Bhattacharya J.Burns S.Paul R.Karam S.Bhunia S.Roy M.R.Choudhury A.K.Singh M.Mani M.Orshansky J.Cong D.Brand R.Bordawekar U.Finkler V.KulandaiSamy G.Carpenter E.Kursun J.D.Warnock M.Scheuermann S.Borkar T.Garibay J.Lotz R.K.Montoye L.N.Reddy S.Krishnaswamy C.Washburn J.Earl J.Keinert R.Jammy A.Jerraya J.M.Rabaey W.C.Rhines D.Varma D.Edwards A.J.Weger P.D.Franzon A.Yang S.V.Kosonocky E.Haritan S.Krolikoski T.Kogel B.D.McCredie J.Shen A.Takach S.Venkataraman S.Griffith A.Oberai R.Madge G.Yeric W.Ng Y.Zorian J.M.Cohn D.S.Kung D.Sylvester A.Srivastava S.H.Kulkarni N.S.Nagaraj M.Gavrielov R.Radojcic P.Rickert H.Stork K.Bernstein P.Andry J.Cann P.G.Emma D.Greenberg W.Haensch M.Ignatowski S.J.Koester J.Magerlein A.M.Young
Talks about:
synthesi (4) challeng (4) perform (3) effici (3) design (3) hot (3) technolog (2) algorithm (2) perspect (2) parallel (2)

Person: Ruchir Puri

DBLP DBLP: Puri:Ruchir

Contributed to:

VLDB 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20112011
DAC 20102010
DAC 20092009
DAC 20082008
DAC 20072007
DAC 20062006
DAC 20052005
DAC 20032003
DAC 19991999
DAC 19941994
DAC 19921992

Wrote 20 papers:

VLDB-2015-ChoBBFKP #algorithm #named #parallel #performance
PARADIS: An Efficient Parallel Algorithm for In-place Radix Sort (MC, DB, RB, UF, VK, RP), pp. 1518–1529.
DATE-2014-PaulKBP #energy #hardware #memory management
Energy-efficient hardware acceleration through computing in the memory (SP, RK, SB, RP), pp. 1–6.
DAC-2013-RoyCPP #parallel #synthesis #towards #trade-off
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures (SR, MRC, RP, DZP), p. 8.
DATE-2013-RenPRKWEK #performance #synthesis
Intuitive ECO synthesis for high performance circuits (HR, RP, LNR, SK, CW, JE, JK), pp. 1002–1007.
DAC-2011-BurnsCKPWS #3d #challenge #design
Design, CAD and technology challenges for future processors: 3D perspectives (JB, GC, EK, RP, JDW, MS), p. 212.
DAC-2010-ChoRXP #network #using
History-based VLSI legalization using network flow (MC, HR, HX, RP), pp. 286–291.
DAC-2010-PuriJJJRRS #challenge
EDA challenges and options: investing for the future (RP, WHJ, RJ, AJ, JMR, WCR, LS), pp. 1–2.
DAC-2009-CongNPJBGRRS #question
Moore’s Law: another casualty of the financial meltdown? (JC, NSN, RP, WHJ, JB, MG, RR, PR, HS), pp. 202–203.
DAC-2009-PuriHKCKMST #challenge
From milliwatts to megawatts: system level power challenge (RP, EH, SK, JC, TK, BDM, JS, AT), pp. 750–751.
DAC-2008-PuriJBGLM #synthesis
Custom is from Venus and synthesis from Mars (RP, WHJ, SB, TG, JL, RKM), p. 992.
DAC-2008-PuriVEWFYK #problem #question
Keeping hot chips cool: are IC thermal problems hot air? (RP, DV, DE, AJW, PDF, AY, SVK), pp. 634–635.
DAC-2007-BernsteinACEGHIKMPY #3d #challenge #design
Interconnects in the Third Dimension: Design Challenges for 3D ICs (KB, PA, JC, PGE, DG, WH, MI, SJK, JM, RP, AMY), pp. 562–567.
DAC-2007-ChoXPP #named
TROY: Track Router with Yield-driven Wire Planning (MC, HX, RP, DZP), pp. 55–58.
Making Manufacturing Work For You (SV, RP, SG, AO, RM, GY, WN, YZ), pp. 107–108.
DAC-2006-SinghMPO #nondeterminism #runtime
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty (AKS, MM, RP, MO), pp. 522–527.
Keeping hot chips cool (RP, LS, SB), pp. 285–288.
DAC-2003-PuriSCKPSSK #performance
Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.
DAC-1999-ChuangP #design #perspective
SOI Digital CMOS VLSI — a Design Perspective (CTC, RP), pp. 709–714.
DAC-1994-PuriG #approach #clustering #composition #synthesis
A Modular Partitioning Approach for Asynchronous Circuit Synthesis (RP, JG), pp. 63–69.
DAC-1992-PuriG #algorithm #performance
An Efficient algorithm for Microword Length Minimization (RP, JG), pp. 651–656.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.