Travelled to:1 × France
4 × USA
Collaborated with:C.J.Alpert H.Ren D.Z.Pan J.Hu S.S.Sapatnekar N.Viswanathan G.Nam C.C.N.Chu W.E.Donath P.Kudva L.Stok L.N.Reddy A.Sullivan K.Chakraborty S.D.Posluszny N.Aoki D.Boerstler P.K.Coulman S.H.Dhong B.K.Flachs H.P.Hofstee N.Kojima O.Kwon K.Lee D.Meltzer K.J.Nowka J.Park J.Peter J.Silberman O.Takahashi
Talks about:placement (3) methodolog (2) design (2) microprocessor (1) transform (1) synthesi (1) frequenc (1) resourc (1) quadrat (1) practic (1)
Person: Paul Villarrubia
DBLP: Villarrubia:Paul
Contributed to:
2007200520012000
2000Wrote 5 papers:
- DAC-2007-ViswanathanNAVRC #named #polynomial
- RQL: Global Placement via Relaxed Quadratic Spreading and Linearization (NV, GJN, CJA, PV, HR, CCNC), pp. 453–458.
- DAC-2005-RenPAV #migration
- Diffusion-based placement migration (HR, DZP, CJA, PV), pp. 515–520.
- DAC-2001-AlpertHSV #resource management
- A Practical Methodology for Early Buffer and Wire Resource Allocation (CJA, JH, SSS, PV), pp. 189–194.
- DAC-2000-PoslusznyABCDFHKKLMNPPSTV #design
- “Timing closure by design”, a high frequency microprocessor design methodology (SDP, NA, DB, PKC, SHD, BKF, HPH, NK, OK, KL, DM, KJN, JP, JP, JS, OT, PV), pp. 712–717.
- DATE-2000-DonathKSVRSC #synthesis
- Transformational Placement and Synthesis (WED, PK, LS, PV, LNR, AS, KC), pp. 194–201.