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Travelled to:
1 × USA
Collaborated with:
S.Iida T.Yasufuku M.Takamiya M.Nomura H.Shinohara T.Sakurai
Talks about:
minimum (1) express (1) voltag (1) logic (1) estim (1) close (1) oper (1) gate (1) form (1) dmin (1)

Person: Hiroshi Fuketa

DBLP DBLP: Fuketa:Hiroshi

Contributed to:

DAC 20112011

Wrote 1 papers:

DAC-2011-FuketaIYTNSS #logic
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates (HF, SI, TY, MT, MN, HS, TS), pp. 984–989.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.