Travelled to:2 × USA
Collaborated with:H.Fuketa S.Iida T.Yasufuku M.Takamiya M.Nomura T.Sakurai M.Kurimoto H.Suzuki R.Akiyama T.Yamanaka H.Ohkuma H.Takata
Talks about:voltag (2) minimum (1) express (1) scheme (1) driven (1) detect (1) adjust (1) stage (1) slack (1) scale (1)
Person: Hirofumi Shinohara
DBLP: Shinohara:Hirofumi
Contributed to:
20112008Wrote 2 papers:
- DAC-2011-FuketaIYTNSS #logic
- A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates (HF, SI, TY, MT, MN, HS, TS), pp. 984–989.
- DAC-2008-KurimotoSAYOTS #detection #fault #optimisation #scalability
- Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling (MK, HS, RA, TY, HO, HT, HS), pp. 884–889.