A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
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Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
DAC, 2011.

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@inproceedings{DAC-2011-FuketaIYTNSS,
	author        = "Hiroshi Fuketa and Satoshi Iida and Tadashi Yasufuku and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",
	booktitle     = "{Proceedings of the 48th Design Automation Conference}",
	doi           = "10.1145/2024724.2024942",
	isbn          = "978-1-4503-0636-2",
	pages         = "984--989",
	publisher     = "{ACM}",
	title         = "{A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates}",
	year          = 2011,
}

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