Travelled to:3 × USA
Collaborated with:Y.Chang H.C.Chien K.Tseng K.Ho H.Tsao J.Liu I.Wu T.Chen T.Kuan
Talks about:analog (6) placement (4) awar (4) rout (3) lithographi (2) pattern (2) current (2) match (2) doubl (2) multilevel (1)
Person: Hung-Chih Ou
DBLP: Ou:Hung=Chih
Contributed to:
201520132012Wrote 6 papers:
- DAC-2015-OuTC #self
- Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography (HCO, KHT, YWC), p. 6.
- DAC-2015-OuTLWC
- Layout-dependent-effects-aware analytical analog placement (HCO, KHT, JYL, IPW, YWC), p. 6.
- DAC-2013-ChienOCKC
- Double patterning lithography-aware analog placement (HCCC, HCO, TCC, TYK, YWC), p. 6.
- DAC-2013-HoOCT #array
- Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits (KHH, HCO, YWC, HFT), p. 6.
- DAC-2013-OuCC
- Simultaneous analog placement and routing with current flow and current density considerations (HCO, HCCC, YWC), p. 6.
- DAC-2012-OuCC #constraints #multi
- Non-uniform multilevel analog routing with matching constraints (HCO, HCCC, YWC), pp. 549–554.