Travelled to:3 × USA
Collaborated with:Y.Chang A.Chakraborty D.Z.Pan H.C.Chien H.Ou T.Kuan M.Hsu Y.Chen C.Huang P.Yuh F.Huang D.Liu
Talks about:placement (4) design (2) size (2) awar (2) mix (2) lithographi (1) nonlinear (1) framework (1) algorithm (1) hierarch (1)
Person: Tung-Chieh Chen
DBLP: Chen:Tung=Chieh
Contributed to:
201320082007Wrote 4 papers:
- DAC-2013-ChienOCKC
- Double patterning lithography-aware analog placement (HCCC, HCO, TCC, TYK, YWC), p. 6.
- DAC-2013-HsuCHCC #design
- Routability-driven placement for hierarchical mixed-size circuit designs (MKH, YFC, CCH, TCC, YWC), p. 6.
- DAC-2008-ChenCP #framework
- An integrated nonlinear placement framework with congestion and porosity aware buffer planning (TCC, AC, DZP), pp. 702–707.
- DAC-2007-ChenYCHL #algorithm #design #metaprogramming #named
- MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs (TCC, PHY, YWC, FJH, DL), pp. 447–452.