`Travelled to:`

1 × France

1 × Germany

18 × USA

`Collaborated with:`

S.Fang H.Ou I.H.Jiang J.Lin M.Hsu H.Chang C.C.Lin H.C.Chien B.Su P.Yuh K.Ho I.Liu J.Fang Y.Ho H.Lee T.Chen M.D.F.Wong Z.Jiang C.Yang K.Tseng S.Chen Y.Su Y.Chuang X.Shih S.Wu Y.Chang Y.Chen C.Huang C.Chang R.Liu T.Lin P.Banerjee S.Chou W.Chen V.Balabanov T.Chen G.Liao C.Hsu H.Liu W.Lee H.Chen J.Jou C.Chen D.F.Wong C.Liu H.K.Chiang J.R.Jiang H.Tsao D.Juan D.Marculescu S.Kim Y.Shin K.Chao M.P.Lin H.Zhang S.S.Sapatnekar T.Ho S.Chen H.Lee J.Hsu H.H.Yang Y.Chang G.Wu S.Wu J.Liu I.Wu C.Chiou C.Wang T.Kuan F.Huang D.Liu H.Chen M.Chiang L.Chen B.Han P.Lee I.Lin C.Shen

`Talks about:`

placement (17) awar (16) rout (15) design (12) base (9) chip (8) driven (7) analog (7) optim (7) use (7)

## Person: Yao-Wen Chang

### DBLP: Chang:Yao=Wen

### Contributed to:

### Wrote 53 papers:

- DAC-2015-ChangLF #challenge
- EUV and e-beam manufacturability: challenges and solutions (YWC, RGL, SYF), p. 6.
- DAC-2015-ChenC #architecture
- Routing-architecture-aware analytical placement for heterogeneous FPGAs (SYC, YWC), p. 6.
- DAC-2015-OuTC #self
- Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography (HCO, KHT, YWC), p. 6.
- DAC-2015-OuTLWC
- Layout-dependent-effects-aware analytical analog placement (HCO, KHT, JYL, IPW, YWC), p. 6.
- DAC-2015-SuC #complexity
- Nanowire-aware routing considering high cut mask complexity (YHS, YWC), p. 6.
- DAC-2014-ChangJC #configuration management #functional #using
- Functional ECO Using Metal-Configurable Gate-Array Spare Cells (HYC, IHRJ, YWC), p. 6.
- DAC-2014-ChenHCCW #metaprogramming
- Routability-Driven Blockage-Aware Macro Placement (YFC, CCH, CHC, YWC, CJW), p. 6.
- DAC-2014-HoC #optimisation #performance #pipes and filters
- A New Asynchronous Pipeline Template for Power and Performance Optimization (KHH, YWC), p. 6.
- DAC-2014-LiuCCJ
- Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification (CYL, HJKC, YWC, JHRJ), p. 6.
- DAC-2014-LiuFC #process #self #using
- Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process (IJL, SYF, YWC), p. 6.
- DAC-2013-ChienOCKC
- Double patterning lithography-aware analog placement (HCCC, HCO, TCC, TYK, YWC), p. 6.
- DAC-2013-FangLC #multi
- Stitch-aware routing for multiple e-beam lithography (SYF, IJL, YWC), p. 6.
- DAC-2013-HoC #multi
- Multiple chip planning for chip-interposer codesign (YKH, YWC), p. 6.
- DAC-2013-HoOCT #array
- Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits (KHH, HCO, YWC, HFT), p. 6.
- DAC-2013-HsuCHCC #design
- Routability-driven placement for hierarchical mixed-size circuit designs (MKH, YFC, CCH, TCC, YWC), p. 6.
- DAC-2013-LinBC #effectiveness #performance
- An efficient and effective analytical placer for FPGAs (THL, PB, YWC), p. 6.
- DAC-2013-OuCC
- Simultaneous analog placement and routing with current flow and current density considerations (HCO, HCCC, YWC), p. 6.
- DAC-2012-ChangJC #configuration management #optimisation #using
- Timing ECO optimization using metal-configurable gate-array spare cells (HYC, IHRJ, YWC), pp. 802–807.
- DAC-2012-ChouHC #design
- Structure-aware placement for datapath-intensive circuit designs (SC, MKH, YWC), pp. 762–767.
- DAC-2012-FangC
- Simultaneous flare level and flare variation minimization with dummification in EUVL (SYF, YWC), pp. 1179–1184.
- DAC-2012-FangCC #algorithm #composition #layout #novel
- A novel layout decomposition algorithm for triple patterning lithography (SYF, YWC, WYC), pp. 1185–1190.
- DAC-2012-LeeC #co-evolution #design
- A chip-package-board co-design methodology (HCL, YWC), pp. 1082–1087.
- DAC-2012-LeeLHCCLS #design
- Obstacle-avoiding free-assignment routing for flip-chip designs (PWL, HCL, YKH, YWC, CFC, IJL, CFS), pp. 1088–1093.
- DAC-2012-OuCC #constraints #multi
- Non-uniform multilevel analog routing with matching constraints (HCO, HCCC, YWC), pp. 549–554.
- DATE-2012-JuanCMC #modelling #optimisation #power management #statistics
- Statistical thermal modeling and optimization considering leakage power variations (DCJ, YLC, DM, YWC), pp. 605–610.
- DAC-2011-ChangJC #functional
- Simultaneous functional and timing ECO (HYC, IHRJ, YWC), pp. 140–145.
- DAC-2011-HsuCB #3d #design
- TSV-aware analytical placement for 3D IC designs (MKH, YWC, VB), pp. 664–669.
- DAC-2010-ChuangKSC #optimisation
- Pulsed-latch aware placement for timing-integrity optimization (YLC, SK, YS, YWC), pp. 280–285.
- DAC-2010-LinC #design
- Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips (CCYL, YWC), pp. 641–646.
- DAC-2010-ShihC #independence #performance #synthesis
- Fast timing-model independent buffered clock-tree synthesis (XWS, YWC), pp. 80–85.
- DAC-2009-FangWC #co-evolution #design
- Flip-chip routing with unified area-I/O pad assignments for package-board co-design (JWF, MDFW, YWC), pp. 336–339.
- DAC-2009-JiangHCC #multi
- Spare-cell-aware multilevel analytical placement (ZWJ, MKH, YWC, KYC), pp. 430–435.
- DAC-2009-LinC #design
- ILP-based pin-count aware design methodology for microfluidic biochips (CCYL, YWC), pp. 258–263.
- DAC-2009-LinZWC
- Thermal-driven analog placement considering device matching (MPHL, HZ, MDFW, YWC), pp. 593–598.
- DAC-2008-ChenLC #predict
- Predictive formulae for OPC with applications to lithography-friendly routing (TCC, GWL, YWC), pp. 510–515.
- DAC-2008-JiangSC #design #scalability
- Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs (ZWJ, BYS, YWC), pp. 167–172.
- DAC-2008-YuhSYC #algorithm
- A progressive-ILP based routing algorithm for cross-referencing biochips (PHY, SSS, CLY, YWC), pp. 284–289.
- DAC-2007-ChenYCHL #algorithm #design #metaprogramming #named
- MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs (TCC, PHY, YWC, FJH, DL), pp. 447–452.
- DAC-2007-FangHC #algorithm #design #integer #linear #programming
- An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design (JWF, CHH, YWC), pp. 606–611.
- DAC-2007-LiuLC #algorithm #approximate #multi #optimisation #using
- A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages (HYL, WPL, YWC), pp. 887–890.
- DAC-2006-ChenCCCH #novel
- Novel full-chip gridless routing considering double-via insertion (HYC, MFC, YWC, LC, BH), pp. 755–760.
- DAC-2006-YuhYC #using
- Placement of digital microfluidic biochips using the t-tree formulation (PHY, CLY, YWC), pp. 931–934.
- DAC-2005-HoCCC #architecture #multi
- Multilevel full-chip routing for the X-based architecture (TYH, CFC, YWC, SJC), pp. 597–602.
- DAC-2005-SuC #algorithm
- An exact jumper insertion algorithm for antenna effect avoidance/fixing (BYS, YWC), pp. 325–328.
- DAC-2004-WuC #analysis #design #network #performance
- Efficient power/ground network analysis for power integrity-driven design methodology (SWW, YWC), pp. 177–180.
- DAC-2003-LeeCHY #multi #scalability #using
- Multilevel floorplanning/placement for large-scale modules using B*-trees (HCL, YWC, JMH, HHY), pp. 812–817.
- DAC-2002-LinC #named #orthogonal
- TCG-S: orthogonal coupling of P*-admissible representations for general floorplans (JML, YWC), pp. 842–847.
- DATE-2002-LinCC #using
- Arbitrary Convex and Concave Rectilinear Module Packing Using TCG (JML, HLC, YWC), pp. 69–75.
- DAC-2001-LinC #graph #named #representation #transitive
- TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans (JML, YWC), pp. 764–769.
- DAC-2000-ChangC #architecture #metric
- An architecture-driven metric for simultaneous placement and global routing for FPGAs (YWC, YTC), pp. 567–572.
- DAC-2000-ChangCWW #representation
- B*-Trees: a new representation for non-slicing floorplans (YCC, YWC, GMW, SWW), pp. 458–463.
- DAC-1999-JiangJC #optimisation #performance
- Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (IHRJ, JYJ, YWC), pp. 90–95.
- DAC-1996-ChenCW #optimisation #performance
- Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation (CPC, YWC, DFW), pp. 405–408.