BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Germany
2 × France
2 × USA
Collaborated with:
N.Dutt N.D.Dutt E.Brockmeyer B.Durinck M.Miranda D.Cho S.Pasricha Y.Paek S.Ko A.Azevedo R.Cornea R.Gupta A.V.Veidenbaum A.Nicolau
Talks about:
memori (3) data (3) hierarchi (2) analysi (2) optim (2) reus (2) multiprocessor (1) checkpoint (1) irregular (1) techniqu (1)

Person: Ilya Issenin

DBLP DBLP: Issenin:Ilya

Contributed to:

LCTES 20082008
DAC 20062006
DATE 20052005
DATE v1 20042004
DATE 20022002

Wrote 5 papers:

LCTES-2008-ChoPIDPK #array #compilation #data access #layout #optimisation
Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
DAC-2006-IsseninBDD #analysis #memory management #multi #reuse
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies (II, EB, BD, ND), pp. 49–52.
DATE-2005-IsseninD #automation #generative #memory management #named #optimisation
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations (II, NDD), pp. 808–813.
DATE-v1-2004-IsseninBMD #analysis #memory management #reuse
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies (II, EB, MM, ND), pp. 202–207.
DATE-2002-AzevedoICGDVN #scheduling #using
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.