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Travelled to:
1 × China
2 × Germany
4 × France
4 × USA
Collaborated with:
A.Nicolau S.Kundu D.Kim S.Ha S.Gupta N.Dutt M.A.Adnan S.Lerner M.K.Ganai J.Coburn T.Bunker M.Schwarz S.Swanson A.Kejariwal N.Bansal A.Leung M.Gupta Y.Agarwal R.Jhala S.Murali A.Mutapcic D.Atienza S.P.Boyd L.Benini G.D.Micheli A.Azevedo I.Issenin R.Cornea N.D.Dutt A.V.Veidenbaum
Talks about:
simul (3) high (3) base (3) use (3) transact (2) synthesi (2) control (2) driven (2) design (2) level (2)

Person: Rajesh Gupta

DBLP DBLP: Gupta:Rajesh

Contributed to:

DATE 20132013
SOSP 20132013
PLDI 20122012
CAV 20082008
DAC 20082008
DATE 20082008
DATE 20072007
DATE 20062006
DAC 20042004
DATE v1 20042004
DATE 20022002

Wrote 12 papers:

DATE-2013-AdnanG #in the cloud
Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity (MAA, RG), pp. 262–265.
SOSP-2013-CoburnBSGS #transaction
From ARIES to MARS: transaction support for next-generation, solid-state drives (JC, TB, MS, RG, SS), pp. 197–212.
PLDI-2012-LeungGAGJL #gpu #kernel #verification
Verifying GPU kernels by test amplification (AL, MG, YA, RG, RJ, SL), pp. 383–394.
CAV-2008-KunduLG #synthesis #validation
Validating High-Level Synthesis (SK, SL, RG), pp. 459–472.
DAC-2008-KunduGG #design #partial order #reduction #scalability #testing
Partial order reduction for scalable testing of systemC TLM designs (SK, MKG, RG), pp. 936–941.
DATE-2008-MuraliMAGBBM #manycore #optimisation #using
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization (SM, AM, DA, RG, SPB, LB, GDM), pp. 110–115.
DATE-2007-KimHG #multi #named #simulation #transaction
CATS: cycle accurate transaction-driven simulation with multiple processor simulators (DK, SH, RG), pp. 749–754.
DATE-2006-KimHG #execution #parallel #using
Parallel co-simulation using virtual synchronization with redundant host execution (DK, SH, RG), pp. 1151–1156.
DAC-2004-KejariwalGNDG #algorithm #clustering #energy #mobile
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices (AK, SG, AN, ND, RG), pp. 556–561.
DATE-v1-2004-BansalGDNG #architecture #configuration management #network
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures (NB, SG, ND, AN, RG), pp. 474–479.
DATE-v1-2004-GuptaDGN #control flow #design #synthesis
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow (SG, ND, RG, AN), pp. 114–121.
DATE-2002-AzevedoICGDVN #scheduling #using
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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