BibSLEIGH — Nikil_D

Travelled to:

1 × Canada
14 × USA
6 × Germany
7 × France

Collaborated with:

A.Nicolau L.A.D.Bathen P.Grun S.Pasricha P.Mishra R.K.Gupta M.Reshadi D.Gajski R.Cornea P.R.Panda P.Biswas I.Issenin A.Shrivastava E.Bozorgzadeh M.Ben-Romdhane A.Halambi S.Gupta S.Banerjee Y.Wang Z.Shao M.Mamidipaka P.K.Jha J.R.Kipps P.Gupta P.Ienne L.Pozzi E.Earlie S.Sarma N.Venkatasubramanian J.Lee K.Choi F.Catthoor C.E.Kozyrakis D.J.Kolson T.Hadley N.Savoiu A.Nicolau H.Tomiyama H.Wang K.Siu B.Balaji M.A.A.Faruque Y.Agarwal T.Muck S.Park Y.Paek S.Kim V.Ganesh A.Khare H.V.Antwerpen S.Mohapatra C.Pereira R.v.Vignau A.Azevedo R.Gupta A.V.Veidenbaum Amir M. Rahmani Bryan Donyanavard Tiago Mück Kasra Moazzemi A.Jantsch O.Mutlu T.Kam M.Kishinevsky S.Rotem

Talks about:

memori (14) architectur (13) synthesi (10) high (9) level (8) awar (8) system (7) processor (6) explor (6) compil (6)

Person: Nikil D. Dutt

DBLP: Dutt:Nikil_D=

Facilitated 1 volumes:

Contributed to:

2015

2012

2011

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1994

1993

1991

1990

1989

2018

Wrote 44 papers:

DAC-2015-BalajiFDGA #abstraction #architecture #cyber-physical #modelling: Models, abstractions, and architectures: the missing links in cyber-physical systems (BB, MAAF, NDD, RKG, YA), p. 6.
DAC-2015-SarmaMBDN #energy #linux #named #performance: SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs (SS, TM, LADB, NDD, AN), p. 6.
DATE-2015-SarmaDGVN #paradigm #self: Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation (SS, NDD, PG, NV, AN), pp. 625–628.
DAC-2012-WangBDS #memory management #metadata #named #reliability: Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems (YW, LADB, NDD, ZS), pp. 214–219.
DATE-2012-BathenDNG #memory management #named #variability: VaMV: Variability-aware Memory Virtualization (LADB, NDD, AN, PG), pp. 284–287.
DATE-2012-WangBSD #3d #memory management #named: 3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory (YW, LADB, ZS, NDD), pp. 1307–1312.
DATE-2011-BathenD #distributed #embedded #named #power management #reliability: E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories (LADB, NDD), pp. 1141–1146.
DATE-2006-BiswasDIP #architecture #automation #functional #identification: Automatic identification of application-specific functional units with architecturally visible storage (PB, NDD, PI, LP), pp. 212–217.
DATE-2006-CorneaND #mobile #optimisation: Software annotations for power optimization on mobile devices (RC, AN, NDD), pp. 684–689.
DATE-2006-PasrichaD #architecture #communication #memory management #named: COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC (SP, NDD), pp. 700–705.
LCTES-2006-ParkSDNPE #reduction #scheduling: Bypass aware instruction scheduling for register file power reduction (SP, AS, NDD, AN, YP, EE), pp. 173–181.
DAC-2005-BanerjeeBD #architecture #clustering #configuration management: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration (SB, EB, NDD), pp. 335–340.
DAC-2005-PasrichaDBB #architecture #automation #communication #synthesis: Floorplan-aware automated synthesis of bus-based communication architectures (SP, NDD, EB, MBR), pp. 565–570.
DATE-2005-BiswasBDPI #generative #named #set: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement (PB, SB, NDD, LP, PI), pp. 1246–1251.
DATE-2005-IsseninD #automation #generative #memory management #named #optimisation: FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations (II, NDD), pp. 808–813.
DATE-2005-MishraD #functional #generative #pipes and filters #testing #validation: Functional Coverage Driven Test Generation for Validation of Pipelined Processors (PM, NDD), pp. 678–683.
DATE-2005-ReshadiD #generative #modelling #performance #pipes and filters: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation (MR, NDD), pp. 786–791.
DATE-2005-ShrivastavaDNE #embedded #framework #named: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors (AS, NDD, AN, EE), pp. 1264–1269.
DAC-2004-PasrichaDB #approach #architecture #communication #modelling #performance #transaction: Extending the transaction level modeling approach for fast communication architecture exploration (SP, NDD, MBR), pp. 113–118.
DATE-v2-2004-AntwerpenDGMPVV #design #energy #multi: Energy-Aware System Design for Wireless Multimedia (HVA, NDD, RKG, SM, CP, NV, RvV), pp. 1124–1131.
DAC-2003-ReshadiMD #flexibility #performance #set #simulation: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation (MR, PM, NDD), pp. 758–763.
DATE-2003-GuptaDGN #branch #design #synthesis: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs (SG, NDD, RKG, AN), pp. 10270–10275.
DATE-2003-MamidipakaD #architecture #embedded #memory management #power management #stack: On-chip Stack Based Memory Organization for Low Power Embedded Architectures (MM, NDD), pp. 11082–11089.
LCTES-2003-LeeCD #algorithm #architecture #configuration management: An algorithm for mapping loops onto coarse-grained reconfigurable architectures (JeL, KC, NDD), pp. 183–188.
DAC-2002-GuptaSDGNKKR #coordination #performance #synthesis: Coordinated transformations for high-level synthesis of high performance microprocessor blocks (SG, NS, NDD, RKG, AN, TK, MK, SR), pp. 898–903.
DATE-2002-AzevedoICGDVN #scheduling #using: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.
DATE-2002-GrunDN #memory management: Memory System Connectivity Exploration (PG, NDD, AN), pp. 894–901.
DATE-2002-HalambiSBDN #compilation #performance #reduction #using: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs (AH, AS, PB, NDD, AN), pp. 402–408.
DATE-2002-MishraDNT #automation #execution #functional #multi #pipes and filters #verification: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units (PM, NDD, AN, HT), pp. 36–43.
DAC-2001-GuptaSKDGN #design #synthesis: Speculation Techniques for High Level Synthesis of Control Intensive Designs (SG, NS, SK, NDD, RKG, AN), pp. 269–272.
DATE-2001-GrunDN #embedded #memory management #power management: Access pattern based local memory customization for low power embedded systems (PG, NDD, AN), pp. 778–784.
DAC-2000-GrunDN #compilation #memory management: Memory aware compilation through accurate timing extraction (PG, NDD, AN), pp. 316–321.
DATE-2000-CatthoorDK #architecture #compilation #data transfer #how #memory management #question: How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? (FC, NDD, CEK), pp. 426–433.
DATE-2000-HalambiCGDN #architecture: Architecture Exploration of Parameterizable EPIC SOC Architectures (AH, RC, PG, NDD, AN), p. 748.
DATE-1999-HalambiGGKDN #architecture #compilation #named: EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability (AH, PG, VG, AK, NDD, AN), pp. 485–490.
DATE-1998-PandaDN #embedded: Data Cache Sizing for Embedded Processor Applications (PRP, NDD, AN), pp. 925–926.
EDTC-1997-JhaD #library: Library mapping for memories (PKJ, NDD), pp. 288–292.
EDTC-1997-PandaDN #embedded #memory management #performance: Efficient utilization of scratch-pad memory in embedded processor applications (PRP, NDD, AN), pp. 7–11.
DAC-1994-KolsonND #memory management #synthesis: Minimization of Memory Traffic in High-Level Synthesis (DJK, AN, NDD), pp. 149–154.
DAC-1993-WangDNS #architecture #multi #scalability #synthesis #using: High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules (HW, NDD, AN, KYS), pp. 336–342.
DAC-1991-DuttK #library #synthesis: Bridging High-Level Synthesis to RTL Technology Libraries (NDD, JRK), pp. 526–529.
DAC-1990-DuttHG #behaviour #representation #synthesis: An Intermediate Representation for Behavioral Synthesis (NDD, TH, DG), pp. 14–19.
DAC-1989-DuttG #behaviour #design #synthesis: Designer Controlled Behavioral Synthesis (NDD, DG), pp. 754–757.
ASPLOS-2018-RahmaniDMMJMD #coordination #manycore #named #resource management: SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management (AMR, BD, TM, KM, AJ, OM, NDD), pp. 169–183.