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Travelled to:
1 × Germany
1 × Italy
2 × France
4 × USA
Collaborated with:
A.Nicolau D.Nicolaescu H.Homayoun S.Pasricha M.A.Makhzan A.Kejariwal C.Badea U.Banerjee C.D.Polychronopoulos J.L.Aragón A.Badulescu R.Cammarota D.Donato M.Madhugiri A.Azevedo I.Issenin R.Cornea R.Gupta N.D.Dutt X.Tian M.Girkar W.Li S.Kozhukhov Zhangxiaowen Gong Zhi Chen 0001 Justin Josef Szaday David C. Wong 0001 Z.Sura Neftali Watkinson S.Maleki D.A.Padua J.Torrellas
Talks about:
embed (5) processor (4) energi (4) perform (3) cach (3) consumpt (2) resourc (2) program (2) improv (2) effici (2)

Person: Alexander V. Veidenbaum

DBLP DBLP: Veidenbaum:Alexander_V=

Contributed to:

CC 20132013
DAC 20082008
LCTES 20082008
PPoPP 20082008
PPoPP 20072007
DATE v2 20042004
DATE 20032003
DATE 20022002
OOPSLA 20182018

Wrote 10 papers:

CC-2013-CammarotaNVKDM #on the #optimisation
On the Determination of Inlining Vectors for Program Optimization (RC, AN, AVV, AK, DD, MM), pp. 164–183.
DAC-2008-HomayounPMV #embedded #energy #performance #scalability
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency (HH, SP, MAM, AVV), pp. 68–71.
LCTES-2008-BadeaNV #embedded #energy #virtual machine
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems (CB, AN, AVV), pp. 23–30.
LCTES-2008-HomayounPMV #adaptation #embedded #energy #performance
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors (HH, SP, MAM, AVV), pp. 71–78.
PPoPP-2008-KejariwalNBVP #clustering
Cache-aware iteration space partitioning (AK, AN, UB, AVV, CDP), pp. 269–270.
PPoPP-2007-KejariwalTGLKBNVP #analysis #concurrent #cpu #performance #specification #thread #using
Tight analysis of the performance potential of thread speculation using spec CPU 2006 (AK, XT, MG, WL, SK, UB, AN, AVV, CDP), pp. 215–225.
DATE-v2-2004-AragonNVB #design #embedded #energy
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors (JLA, DN, AVV, AMB), pp. 1374–1375.
DATE-2003-NicolaescuVN #embedded #power management
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors (DN, AVV, AN), pp. 11064–11069.
DATE-2002-AzevedoICGDVN #scheduling #using
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.
OOPSLA-2018-GongCS0SWMPVNT #compilation #empirical
An empirical study of the effect of source-level loop transformations on compiler stability (ZG, ZC0, JJS, DCW0, ZS, NW, SM, DAP, AVV, AN, JT), p. 29.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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