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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
R.Vemuri M.Kaul S.Govindarajan
Talks about:
reconfigur (3) synthesi (2) comput (2) fpga (2) base (2) hierarch (1) approach (1) resourc (1) fission (1) environ (1)

Person: Iyad Ouaiss

DBLP DBLP: Ouaiss:Iyad

Contributed to:

DATE 20012001
DATE 20002000
DAC 19991999

Wrote 3 papers:

DATE-2001-OuaissV #configuration management #memory management #synthesis
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers (IO, RV), pp. 650–657.
DATE-2000-OuaissV #configuration management #performance
Efficient Resource Arbitration in Reconfigurable Computing Environments (IO, RV), pp. 560–566.
DAC-1999-KaulVGO #approach #automation #clustering #configuration management #synthesis
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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