BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × France
2 × USA
Collaborated with:
A.J.Strojwas K.Brock C.Edwards R.Lannoo U.Schlichtmann A.Domic D.Overhauser M.Kliment
Talks about:
time (3) design (2) verif (2) power (2) construct (1) synthesi (1) strategi (1) interact (1) perform (1) signal (1)

Person: Jacques Benkoski

DBLP DBLP: Benkoski:Jacques

Contributed to:

DATE 20022002
DAC 19911991
DAC 19891989

Wrote 3 papers:

DATE-2002-BrockELSDBOK #design #power management
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs (KB, CE, RL, US, AD, JB, DO, MK), p. 538.
DAC-1991-BenkoskiS #layout #synthesis #verification
The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
DAC-1989-BenkoskiS #interactive #modelling #multi #verification
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator (JB, AJS), pp. 668–673.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.