BibSLEIGH — Andrzej_J

Travelled to:

13 × USA
3 × France

Collaborated with:

L.T.Pileggi J.Benkoski ∅ Y.Liu V.Kheterpal V.Rovner K.W.Michaels M.Sivaraman M.P.Chew X.Li D.Pandini D.M.H.Walker C.S.Kellen R.C.Aitken T.Jhaveri S.R.Nassif V.Koval I.W.Farmaga S.W.Director W.Zhang S.Saxena R.A.Rutenbar Y.Zhan D.Newmark M.Sharma T.G.Hersan D.Motiani Y.Takegawa N.Ns J.C.Rey J.Kawa C.Lütkemeyer V.Pitchumani S.Trimberger M.Casale-Rossi A.Domic C.Guardiani P.Magarshack D.Pattullo J.Sawicki H.Schmit P.Gopalakrishnan A.Koorapaty C.Patel K.Y.Tong

Talks about:

time (7) simul (5) model (4) interconnect (3) regular (3) analysi (3) variat (3) design (3) logic (3) manufactur (2)

Person: Andrzej J. Strojwas

DBLP: Strojwas:Andrzej_J=

Contributed to:

2013

2010

2009

2007

2005

2004

2003

2002

2000

1999

1998

1994

1991

1989

1985

Wrote 21 papers:

DAC-2013-ZhangLSSR #automation #clustering: Automatic clustering of wafer spatial signatures (WZ, XL, SS, AJS, RAR), p. 6.
DAC-2010-NSRKALPST #problem #question #variability: Who solves the variability problem? (NN, JCR, JK, RCA, CL, VP, AJS, ST), pp. 218–219.
DAC-2009-StrojwasJRP #using: Creating an affordable 22nm node using design-lithography co-optimization (AJS, TJ, VR, LTP), pp. 95–96.
DATE-2007-Casale-RossiSADGMPS #named #product line #question #trust: DFM/DFY: should you trust the surgeon or the family doctor? (MCR, AJS, RCA, AD, CG, PM, DP, JS), pp. 439–442.
DAC-2005-KheterpalRHMTSP #design: Design methodology for IC manufacturability based on regular logic-bricks (VK, VR, TGH, DM, YT, AJS, LTP), pp. 353–358.
DAC-2005-ZhanSLPNS #analysis #statistics: Correlation-aware statistical timing analysis with non-gaussian delay distributions (YZ, AJS, XL, LTP, DN, MS), pp. 77–82.
DAC-2004-KheterpalSP #architecture: Routing architecture exploration for regular fabrics (VK, AJS, LTP), pp. 204–207.
DAC-2003-PileggiSSGKKPRT #trade-off: Exploring regular fabrics to optimize the performance-cost trade-off (LTP, HS, AJS, PG, VK, AK, CP, VR, KYT), pp. 782–787.
DATE-2002-PandiniPS #logic #synthesis: Congestion-Aware Logic Synthesis (DP, LTP, AJS), pp. 664–671.
DAC-2000-LiuNPS: Impact of interconnect variations on the clock skew of a gigahertz microprocessor (YL, SRN, LTP, AJS), pp. 168–171.
DAC-1999-LiuPS #analysis: Model Order-Reduction of RC(L) Interconnect Including Variational Analysis (YL, LTP, AJS), pp. 201–206.
DAC-1998-LiuPS #modelling #named #order: ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models (YL, LTP, AJS), pp. 469–472.
DAC-1994-KovalFSD #named: MONSTR: A Complete Thermal Simulator of Electronic Systems (VK, IWF, AJS, SWD), pp. 570–575.
EDAC-1994-MichaelsS #modelling #simulation: Variable Accuracy Device Modeling for Event-Driven Circuit Simulation (KWM, AJS), pp. 557–561.
EDAC-1994-SivaramanS #analysis #parametricity #towards: Towards Incorporating Device Parameter Variations in Timing Analysis (MS, AJS), pp. 338–342.
DAC-1991-BenkoskiS #layout #synthesis #verification: The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
DAC-1991-ChewS #logic #multi #simulation: Utilizing Logic Information in Multi-Level Timing Simulation (MPC, AJS), pp. 215–218.
DAC-1991-WalkerKS #database #editing #process #representation #statistics: A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator (DMHW, CSK, AJS), pp. 579–584.
DAC-1989-BenkoskiS #interactive #modelling #multi #verification: Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator (JB, AJS), pp. 668–673.
DAC-1989-Strojwas #design: Design for Manufacturability and Yield (AJS), pp. 454–459.
DAC-1985-Strojwas: CMU-CAM system (AJS), pp. 319–325.