BibSLEIGH — Ulf_Schlichtmann

Travelled to:

4 × Germany
6 × France
6 × USA

Collaborated with:

D.Müller-Gritschneder H.E.Graeb K.Lu D.Mueller V.Kleeberger B.Li U.Rührmair V.Todorov H.Reinig M.Jassi P.R.Maier W.Burleson C.Knoth H.Jedda T.Massier F.Brglez M.Hermann M.Schmidt J.Haase S.Chakraborty T.Tseng T.Ho G.Georgakos R.Schneider M.Pronath J.Zou G.Stehr R.Kumar Y.Shen J.Hu E.Wallander M.Greim Q.Chen G.Csaba P.Lugli N.Chen W.Schneider C.Piguet J.Gautier C.Heer I.O'Connor A.Lange C.Sohrmann R.Jancke I.Lorenz H.Kinzelbach V.Glöckel M.Dietrich U.Eichler M.Bühler J.Koehl J.Bickford J.Hibbeler R.Sommer A.Ripp K.Brock C.Edwards R.Lannoo A.Domic J.Benkoski D.Overhauser M.Kliment J.A.Abraham A.Evans C.Gimmler-Dumont M.Glaß A.Herkersdorf S.R.Nassif N.Wehn J.Oetjens N.Bannow M.Becker O.Bringmann A.Burger M.Chaari R.Drechsler W.Ecker K.Grüttner T.Kruse C.Kuznik H.M.Le M.Mauderer W.Müller F.Poppen H.Post S.Reiter W.Rosenstiel S.Roth A.v.Schwerin B.Tabacaru A.Viehl

Talks about:

design (10) time (8) power (5) model (5) technolog (4) circuit (4) analog (4) level (4) prototyp (3) virtual (3)

Person: Ulf Schlichtmann

DBLP: Schlichtmann:Ulf

Contributed to:

2015

2014

2013

2012

2009

2008

2007

2006

2005

2004

2002

1992

Wrote 28 papers:

DAC-2015-JassiMS #design #grammarware #integration #named: GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs (MJ, DMG, US), p. 6.
DAC-2015-TsengLHS #synthesis: Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping (TMT, BL, TYH, US), p. 6.
DATE-2015-KumarLSSH #adaptation #verification: Timing verification for adaptive integrated circuits (RK, BL, YS, US, JH), pp. 1587–1590.
DAC-2014-KleebergerMS #analysis: Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience (VK, PRM, US), p. 6.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using: Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2014-LangeSJHLS #correlation #modelling #parametricity #probability #standard: Probabilistic standard cell modeling considering non-Gaussian parameters and correlations (AL, CS, RJ, JH, IL, US), pp. 1–4.
DATE-2014-RuhrmairSB #how: Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks (UR, US, WB), pp. 1–4.
DATE-2014-SchlichtmannKAEGGHNW #abstraction #design: Connecting different worlds — Technology abstraction for reliability-aware design and Test (US, VK, JAA, AE, CGD, MG, AH, SRN, NW), pp. 1–8.
DAC-2013-GeorgakosSSC #architecture #challenge #reliability: Reliability challenges for electric vehicles: from devices to architecture and systems software (GG, US, RS, SC), p. 9.
DAC-2013-KleebergerGS #evaluation #modelling #performance #predict #standard: Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies (VK, HEG, US), p. 6.
DATE-2013-LuMS #embedded #performance #simulation: Fast cache simulation for host-compiled simulation of embedded software (KL, DMG, US), pp. 637–642.
DATE-2013-LuMS13a #estimation: Analytical timing estimation for temporally decoupled TLMs considering resource conflicts (KL, DMG, US), pp. 1161–1166.
DATE-2013-Mueller-GritschnederLWGS #case study #framework #platform #prototype #realtime: A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot (DMG, KL, EW, MG, US), pp. 1331–1334.
DATE-2013-TodorovMRS #approach #clustering #synthesis: A spectral clustering approach to application-specific network-on-chip synthesis (VT, DMG, HR, US), pp. 1783–1788.
DATE-2012-ChenCLSR: Characterization of the bistable ring PUF (QC, GC, PL, US, UR), pp. 1459–1462.
DATE-2012-KnothJS #analysis #modelling: Current source modeling for power and timing analysis at different supply voltages (CK, HJ, US), pp. 923–928.
DATE-2012-LuMS #abstraction #modelling #prototype #transaction: Accurately timed transaction level models for virtual prototyping at high abstraction level (KL, DMG, US), pp. 135–140.
DATE-2012-TodorovMRS #approximate #automation #memory management #transaction: Automated construction of a cycle-approximate transaction level model of a memory controller (VT, DMG, HR, US), pp. 1066–1071.
DATE-2009-LiCSSS #analysis #on the #statistics: On hierarchical statistical static timing analysis (BL, NC, MS, WS, US), pp. 1320–1325.
DATE-2009-SchlichtmannSKPGDEH #design #how #statistics: Digital design at a crossroads How to make statistical design methodologies industrially relevant (US, MS, HK, MP, VG, MD, UE, JH), pp. 1542–1547.
DATE-2008-MassierGS #design: Sizing Rules for Bipolar Analog Circuit Design (TM, HEG, US), pp. 140–145.
DATE-2007-MuellerGS #design #polynomial #programming #trade-off #using: Trade-off design of analog circuits using goal attainment and “Wave Front” sequential quadratic programming (DM, HEG, US), pp. 75–80.
DAC-2006-ZouMGS #optimisation: A CPPLL hierarchical optimization methodology considering jitter, power and locking time (JZ, DM, HEG, US), pp. 19–24.
DATE-2006-BuhlerKBHSSPR #design #process: DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
DAC-2005-MuellerSGS #performance: Deterministic approaches to analog performance space exploration (PSE) (DM, GS, HEG, US), pp. 869–874.
DATE-v1-2004-PiguetGHOS #logic #power management: Extremely Low-Power Logic (CP, JG, CH, IO, US), pp. 656–663.
DATE-2002-BrockELSDBOK #design #power management: Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs (KB, CE, RL, US, AD, JB, DO, MK), p. 538.
DAC-1992-SchlichtmannBH #agile: Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping (US, FB, MH), pp. 374–379.