Travelled to:1 × France
1 × Germany
1 × USA
Collaborated with:C.Ong K.Cheng K.Chou M.Lu X.Huang H.Chang D.Kwai K.(.Cheng C.Wu
Talks about:scheme (2) adc (2) techniqu (1) robust (1) toler (1) error (1) count (1) test (1) imag (1) code (1)
Person: Jiun-Lang Huang
DBLP: Huang:Jiun=Lang
Contributed to:
2010
20102000Wrote 3 papers:
- DAC-2010-ChangHKCW #3d #fault
- An error tolerance scheme for 3D CMOS imagers (HMC, JLH, DMK, KT(C, CWW), pp. 917–922.
- DATE-2010-HuangCLH #robust
- A robust ADC code hit counting technique (JLH, KYC, MHL, XLH), pp. 1749–1754.
- DATE-2000-HuangOC #testing
- A BIST Scheme for On-Chip ADC and DAC Testing (JLH, CKO, KTC), pp. 216–220.