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Travelled to:
1 × France
2 × USA
Collaborated with:
C.Lung Y.Ho S.Chang H.Chang J.Huang K.(.Cheng C.Wu S.Huang Y.Lin K.Tsai W.Cheng S.K.Sunter Y.Chou
Talks about:
throughput (1) processor (1) thermal (1) scheme (1) toler (1) small (1) optim (1) multi (1) error (1) delay (1)

Person: Ding-Ming Kwai

DBLP DBLP: Kwai:Ding=Ming

Contributed to:

DAC 20122012
DATE 20112011
DAC 20102010

Wrote 3 papers:

DAC-2012-HuangLTCSCK #3d #testing
Small delay testing for TSVs in 3-D ICs (SYH, YHL, KHT, WTC, SKS, YFC, DMK), pp. 1031–1036.
DATE-2011-LungHKC #3d #manycore #online #optimisation #throughput
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization (CLL, YLH, DMK, SCC), pp. 8–13.
DAC-2010-ChangHKCW #3d #fault
An error tolerance scheme for 3D CMOS imagers (HMC, JLH, DMK, KT(C, CWW), pp. 917–922.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.