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Travelled to:
21 × USA
6 × Germany
7 × France
Collaborated with:
L.Wang M.Marek-Sadowska A.Krstic V.D.Agrawal Y.Jiang K.Chen J.Liou A.S.Krishnakumar G.Parthasarathy M.K.Iyer S.Huang S.Chang M.C.Chao A.Ghofrani W.Lai M.T.Lee F.Lu T.Huang C.Ong H.Tsai S.Bhawmik M.A.Lastras-Montaño D.Hong S.(.Pan Y.Lin K.Yang Y.Chang C.Huang H.Chen H.T.Ma I.Pomeranz T.M.Mak M.S.Abadir S.Dey D.Chang C.Lin S.Wang S.T.Chakradhar W.Wei A.Rahimi L.Benini R.K.Gupta C.Lo P.Wang H.Chang K.Goh E.Y.Chang J.Huang S.Devadas K.Keutzer P.Agrawal H.Tseng C.Kung S.Saberi C.P.Yue F.Brewer T.Feng C.Lin R.C.Huang S.Kundu M.Rodgers K.Roy J.J.Lu C.Lin D.I.Cheng D.C.Wang T.Lee U.Sparmann D.Luxenburger S.M.Reddy N.S.Woo S.Zhang F.Lin C.Hsu H.Wang M.Abbas Y.Furukawa S.Komatsu K.Asada C.Chiang J.Hou J.Moondanos Z.Hanna L.Chen T.Aikyo Y.Zheng P.Lisherness M.Gao J.Bovington S.Yang K.Fukuda Y.Yeh T.Sekitani T.Someya J.Dworak M.R.Mercer R.Kapur T.W.Williams
Talks about:
test (28) base (13) effici (10) circuit (9) fault (9) delay (9) time (8) generat (7) function (6) diagnosi (6)

Person: Kwang-Ting Cheng

DBLP DBLP: Cheng:Kwang=Ting

Contributed to:

DATE 20152015
DAC 20142014
DATE 20142014
DATE 20122012
DATE 20112011
DATE 20102010
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v1 20042004
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
CIKM 20012001
DAC 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997
DAC 19961996
DAC 19951995
DAC 19941994
DAC 19931993
DAC 19921992
DAC 19911991
DAC 19901990
DAC 19881988

Wrote 65 papers:

DATE-2015-Lastras-Montano #configuration management #hybrid #memory management #named
HReRAM: a hybrid reconfigurable resistive random-access memory (MALM, AG, KTC), pp. 1299–1304.
DATE-2015-RahimiGCBG #approximate #energy #memory management
Approximate associative memristive memory for energy-efficient GPUs (AR, AG, KTC, LB, RKG), pp. 1497–1502.
DAC-2014-RahimiGLCBG #architecture #collaboration #compilation #energy
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing (AR, AG, MALM, KTC, LB, RKG), p. 6.
DATE-2014-ZhangLHCW #multi #performance #predict
Joint Virtual Probe: Joint exploration of multiple test items’ spatial patterns for efficient silicon characterization and test prediction (SZ, FL, CKH, KTC, HW), pp. 1–6.
DATE-2012-ZhengLGBYC #communication #configuration management #power management
Power-efficient calibration and reconfiguration for on-chip optical communication (YZ, PL, MG, JB, SY, KTC), pp. 1501–1506.
DATE-2011-WangCC #self
An all-digital built-in self-test technique for transfer function characterization of RF PLLs (PYW, HMC, KTC), pp. 359–364.
DATE-2010-AbbasCFKA #adaptation #automation #framework #generative #performance #testing
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links (MA, KTC, YF, SK, KA), pp. 1755–1760.
DATE-2010-HuangFLYSSC #design #flexibility #named #novel #pseudo
Pseudo-CMOS: A novel design style for flexible electronics (TCH, KF, CML, YHY, TS, TS, KTC), pp. 154–159.
DATE-2010-LoHCHC #flexibility #multi
A portable multi-pitch e-drum based on printed flexible pressure sensors (CML, TCH, CYC, JH, KTC), pp. 1082–1087.
DAC-2007-HuangTKC #analysis #case study #flexibility #reliability
Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver (TCH, HYT, CPK, KTC), pp. 966–969.
DATE-2007-HongSCY #adaptation
A two-tone test method for continuous-time adaptive equalizers (DH, SS, KTC, CPY), pp. 1283–1288.
DATE-2007-PanC #analysis #component #fault #framework #quality #reliability
A framework for system reliability analysis considering both system error tolerance and component test quality (SJ(RP, KTC), pp. 1581–1586.
DAC-2006-ChaoCWCW #analysis #using
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors (MCTC, KTC, SW, STC, WW), pp. 1083–1088.
DATE-2006-ChaoWCWC #using
Coverage loss by using space compactors in presence of unknown values (MCTC, SW, STC, WW, KTC), pp. 1053–1054.
DATE-2006-LinC #multi
Multiple-fault diagnosis based on single-fault activation and single-output observation (YCL, KTC), pp. 424–429.
DATE-2006-YangC #fault
Timing-reasoning-based delay fault diagnosis (KY, KTC), pp. 418–423.
DAC-2005-ParthasarathyICB #learning
Structural search for RTL with predicate learning (GP, MKI, KTC, FB), pp. 451–456.
DATE-2005-IyerPC #constraints #learning #performance #theorem proving
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver (MKI, GP, KTC), pp. 666–671.
DATE-2005-LuIPWCC #performance #satisfiability
An Efficient Sequential SAT Solver With Improved Search Strategies (FL, MKI, GP, LCW, KTC, KCC), pp. 1102–1107.
DAC-2004-ParthasarathyICW #constraints #performance #theorem proving
An efficient finite-domain constraint solver for circuits (GP, MKI, KTC, LCW), pp. 212–217.
DAC-2004-WangMCA #learning #on the
On path-based learning and its applications in delay test and diagnosis (LCW, TMM, KTC, MSA), pp. 492–497.
DATE-v1-2004-FengWCL #clustering #simulation
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning (TF, LCW, KTC, CCL), pp. 42–49.
DATE-v1-2004-OngHCW #multi #random
Random Jitter Extraction Technique in a Multi-Gigahertz Signal (CKO, DH, KTC, LCW), pp. 286–291.
DATE-v2-2004-MangoCWC #fault #testing
Pattern Selection for Testing of Deep Sub-Micron Timing Defects (MCTC, LCW, KTC), p. 160.
DAC-2003-KrsticWCLM #fault #modelling #statistics
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models (AK, LCW, KTC, JJL, TMM), pp. 668–673.
DAC-2003-LuWCMH #case study #correlation #industrial
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases (FL, LCW, KTC, JM, ZH), pp. 436–441.
DATE-2003-KrsticWCLA #fault #modelling #statistics
Delay Defect Diagnosis Based Upon Statistical Timing Models — The First Step (AK, LCW, KTC, JJL, MSA), pp. 10328–10335.
DATE-2003-LuWCH #correlation #learning #satisfiability
A Circuit SAT Solver With Signal Correlation Guided Learning (FL, LCW, KTC, RCYH), pp. 10892–10897.
DAC-2002-ChangC #implementation #self #verification
Self-referential verification of gate-level implementations of arithmetic circuits (YTC, KTC), pp. 311–316.
DAC-2002-KrsticLCCD #design #embedded #self
Embedded software-based self-testing for SoC design (AK, WCL, KTC, LC, SD), pp. 355–360.
DAC-2002-LiouKWC #analysis #performance #statistics #testing #validation
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation (JJL, AK, LCW, KTC), pp. 566–569.
DAC-2002-LiouWCDMKW #fault #multi #performance #testing #using
Enhancing test efficiency for delay fault testing using multiple-clocked schemes (JJL, LCW, KTC, JD, MRM, RK, TWW), pp. 371–374.
CIKM-2001-GohCC #classification #image
SVM Binary Classifier Ensembles for Image Classification (KG, EYC, KTC), pp. 395–402.
DAC-2001-LaiC #testing
Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
DAC-2001-LiouCKK #analysis #performance #probability #statistics
Fast Statistical Timing Analysis By Probabilistic Event Propagation (JJL, KTC, SK, AK), pp. 661–666.
DAC-2000-ChuengDRR #challenge
Test challenges for deep sub-micron technologies (KTC, SD, MR, KR), pp. 142–149.
DAC-2000-HuangC #composition #constraints
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques (CYH, KTC), pp. 118–123.
DATE-2000-HuangOC #testing
A BIST Scheme for On-Chip ADC and DAC Testing (JLH, CKO, KTC), pp. 216–220.
DAC-1999-JiangC #analysis #performance #power management
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices (YMJ, KTC), pp. 760–765.
DAC-1999-TsaiCB #quality #using
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme (HCT, KTC, SB), pp. 748–753.
DAC-1998-HuangCCL #design #fault
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits (SYH, KTC, KCC, JYJL), pp. 632–637.
DATE-1998-ChangCML #functional #testing
Functional Scan Chain Testing (DC, KTC, MMS, MTCL), pp. 278–283.
DATE-1998-JiangC #approximate #estimation
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits (YMJ, KTC), pp. 698–702.
DAC-1997-ChangLMAC #approach #synthesis
A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
DAC-1997-JiangKCM #logic #optimisation #performance
Post-Layout Logic Restructuring for Performance Optimization (YMJ, AK, KTC, MMS), pp. 662–665.
DAC-1997-KrsticC #generative
Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits (AK, KTC), pp. 383–388.
DAC-1997-TsaiCLB #algorithm #hybrid
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST (HCT, KTC, CJL, SB), pp. 478–483.
DAC-1996-ChengCWM #estimation #hybrid
A New Hybrid Methodology for Power Estimation (DIC, KTC, DCW, MMS), pp. 439–444.
DAC-1996-HuangCC #fault #verification
Error Correction Based on Verification Techniques (SYH, KCC, KTC), pp. 258–261.
DAC-1996-HuangCCL #generative #simulation
Compact Vector Generation for Accurate Power Simulation (SYH, KCC, KTC, TCL), pp. 161–164.
DAC-1996-LinMCL #logic
Test Point Insertion: Scan Paths through Combinational Logic (CCL, MMS, KTC, MTCL), pp. 268–273.
DAC-1995-ChangMC #algorithm #performance #set
An Efficient Algorithm for Local Don’t Care Sets Calculation (SCC, MMS, KTC), pp. 663–667.
DAC-1995-LinCCMC #logic #synthesis
Logic Synthesis for Engineering Change (CCL, KCC, SCC, MMS, KTC), pp. 647–652.
DAC-1995-SparmannLCR #fault #identification #performance #robust
Fast Identification of Robust Dependent Path Delay Faults (US, DL, KTC, SMR), pp. 119–125.
DAC-1994-ChangCWM #layout #logic #synthesis
Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
DAC-1994-ChengC #fault #generative #quality #testing
Generation of High Quality Non-Robust Tests for Path Delay Faults (KTC, HCC), pp. 365–369.
DAC-1994-KrishnakumarC #hybrid #modelling #on the #set
On the Computation of the Set of Reachable States of Hybrid Models (ASK, KTC), pp. 615–621.
DAC-1993-ChengK #automation #finite #functional #generative #state machine #testing #using
Automatic Functional Test Generation Using the Extended Finite State Machine Model (KTC, ASK), pp. 86–91.
DAC-1992-ChengM #algorithm #on the #problem
On the Over-Specification Problem in Sequential ATPG Algorithms (KTC, HKTM), pp. 16–21.
DAC-1992-PomeranzC #using
State Assignment Using Input/Output Functions (IP, KTC), pp. 573–577.
DAC-1991-Cheng #on the
On Removing Redundancy in Sequential Circuits (KTC), pp. 164–169.
DAC-1991-ChengDK #design #generative #robust #standard #synthesis #testing
Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology (KTC, SD, KK), pp. 80–86.
DAC-1990-AgrawalC #specification #synthesis
Test Function Specification in Synthesis (VDA, KTC), pp. 235–240.
DAC-1990-ChengA #complexity #multi
An Entropy Measure for the Complexity of Multi-Output Boolean Functions (KTC, VDA), pp. 302–305.
DAC-1988-AgrawalCA #concurrent #contest #generative #named
Contest: A Concurrent Test Generator for Sequential Circuits (VDA, KTC, PA), pp. 84–89.

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