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Travelled to:
2 × USA
Collaborated with:
C.Visweswariah K.Ravindran S.G.Walker S.Narayan J.A.G.Jess S.R.Naidu R.H.J.M.Otten
Talks about:
statist (2) time (2) increment (1) parametr (1) predict (1) circuit (1) analysi (1) integr (1) yield (1) order (1)

Person: K. Kalafala

DBLP DBLP: Kalafala:K=

Contributed to:

DAC 20042004
DAC 20032003

Wrote 2 papers:

DAC-2004-VisweswariahRKWN #analysis #first-order #incremental #statistics
First-order incremental block-based statistical timing analysis (CV, KR, KK, SGW, SN), pp. 331–336.
DAC-2003-JessKNOV #parametricity #predict #statistics
Statistical timing for parametric yield prediction of digital integrated circuits (JAGJ, KK, SRN, RHJMO, CV), pp. 932–937.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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