Travelled to:2 × USA
Collaborated with:P.Restle A.E.Ruehli C.Visweswariah K.Ravindran K.Kalafala S.Narayan
Talks about:increment (1) statist (1) analysi (1) induct (1) design (1) speed (1) order (1) first (1) block (1) time (1)
Person: Steven G. Walker
DBLP: Walker:Steven_G=
Contributed to:
20041999Wrote 2 papers:
- DAC-2004-VisweswariahRKWN #analysis #first-order #incremental #statistics
- First-order incremental block-based statistical timing analysis (CV, KR, KK, SGW, SN), pp. 331–336.
- DAC-1999-RestleRW #design #performance
- Dealing with Inductance in High-Speed Chip Design (PR, AER, SGW), pp. 904–909.