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Travelled to:
2 × Germany
3 × USA
Collaborated with:
C.Legl B.Wurth U.Seidl F.M.Johannes K.Antreich J.C.Madre P.Zepter
Talks about:
multipl (3) retim (3) approach (2) perform (2) direct (2) class (2) decomposit (1) technolog (1) placement (1) algorithm (1)

Person: Klaus Eckl

DBLP DBLP: Eckl:Klaus

Contributed to:

DATE 20032003
DAC 19991999
DATE 19991999
DAC 19961996
DAC 19951995

Wrote 5 papers:

DATE-2003-SeidlEJ #using
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information (US, KE, FMJ), pp. 10770–10777.
DAC-1999-EcklMZL #approach #multi
A Practical Approach to Multiple-Class Retiming (KE, JCM, PZ, CL), pp. 237–242.
DATE-1999-EcklL #multi
Retiming Sequential Circuits with Multiple Register Classes (KE, CL), p. 650–?.
DAC-1996-LeglWE #approach #design
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs (CL, BW, KE), pp. 730–733.
DAC-1995-WurthEA #algorithm #composition #functional #multi
Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm (BW, KE, KA), pp. 54–59.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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