Travelled to:3 × USA
Collaborated with:Y.Nakamura M.Tagata T.Okamoto S.Tawada K.Hosokawa I.Kuroda T.Yoshimura H.Ichiryu H.Tanishita S.Suzuki N.Nomizu A.Kondoh
Talks about:method (2) hierarch (1) communic (1) softwar (1) perform (1) hardwar (1) circuit (1) system (1) regist (1) design (1)
Person: Ko Yoshikawa
DBLP: Yoshikawa:Ko
Contributed to:
200620041991Wrote 3 papers:
- DAC-2006-NakamuraTOTY #design #scalability
- Budgeting-free hierarchical design method for large scale and high-performance LSIs (YN, MT, TO, ST, KY), pp. 955–958.
- DAC-2004-NakamuraHKYY #c #c++ #communication #hardware #performance #using
- A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.
- DAC-1991-YoshikawaITSNK #optimisation
- Timing Optimization on Mapped Circuits (KY, HI, HT, SS, NN, AK), pp. 112–117.