Travelled to:1 × China
1 × France
6 × USA
Collaborated with:Y.Nakamura M.Edahiro ∅ M.Chiang T.Okamoto P.Guo C.Cheng T.Yamazoe M.Etoh K.Tsujino T.Fujii Y.Mima T.Matsuda K.Hosokawa I.Kuroda K.Yoshikawa
Talks about:placement (2) circuit (2) channel (2) router (2) regist (2) method (2) rout (2) cell (2) new (2) represent (1)
Person: Takeshi Yoshimura
DBLP: Yoshimura:Takeshi
Contributed to:
2011
2009
200419991995199219901984Wrote 8 papers:
- ICDAR-2011-YamazoeEYT #approach #finite #recognition #transducer
- Hypothesis Preservation Approach to Scene Text Recognition with Weighted Finite-State Transducer (TY, ME, TY, KT), pp. 359–363.
- DATE-2009-ChiangOY
- Register placement for high-performance circuits (MFC, TO, TY), pp. 1470–1475.
- DAC-2004-NakamuraHKYY #c #c++ #communication #hardware #performance #using
- A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.
- DAC-1999-GuoCY #representation
- An O-Tree Representation of Non-Slicing Floorplan and Its Applications (PNG, CKC, TY), pp. 268–273.
- DAC-1995-NakamuraY #clustering #logic #matrix #optimisation #scalability
- A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix (YN, TY), pp. 653–657.
- DAC-1992-FujiiMMY #multi
- A Multi-Layer Channel Router with New Style of Over-the-Cell Routing (TF, YM, TM, TY), pp. 585–588.
- DAC-1990-EdahiroY #algorithm #standard
- New Placement and Global Routing Algorithms for Standard Cell Layouts (ME, TY), pp. 642–645.
- DAC-1984-Yoshimura #performance
- An efficient channel router (TY), pp. 38–44.