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Travelled to:
2 × USA
Collaborated with:
T.Sasaki S.Takasaki H.Ishikura N.Koike K.Yoshikawa H.Ichiryu H.Tanishita S.Suzuki A.Kondoh A.Yamada S.Kato T.Nakazawa K.Tomita
Talks about:
mix (3) system (2) simul (2) logic (2) level (2) hardwar (1) circuit (1) verif (1) optim (1) digit (1)

Person: Nobuyoshi Nomizu

DBLP DBLP: Nomizu:Nobuyoshi

Contributed to:

DAC 19911991
DAC 19861986
DAC 19801980

Wrote 3 papers:

DAC-1991-YoshikawaITSNK #optimisation
Timing Optimization on Mapped Circuits (KY, HI, HT, SS, NN, AK), pp. 112–117.
DAC-1986-TakasakiSNIK #hardware #logic #simulation
HAL II: a mixed level hardware logic simulation system (ST, TS, NN, HI, NK), pp. 581–587.
DAC-1980-SasakiYKNTN #logic #named #scalability #verification
MIXS: A mixed level simulator for large digital system logic verification (TS, AY, SK, TN, KT, NN), pp. 626–633.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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