Travelled to:1 × China
1 × Germany
2 × USA
Collaborated with:D.B.Whalley A.Bardizbanyan P.Larsson-Edefors P.Gavin G.Uh R.Baird Kim-Anh Tran A.Jimborean T.E.Carlson K.Koukos S.Kaxiras S.A.McKee P.Stenström I.Finlayson B.Davis G.S.Tyson
Talks about:data (4) improv (3) effici (3) access (3) pipelin (2) static (2) load (2) use (2) architectur (1) processor (1)
Person: Magnus Själander
DBLP: Sj=auml=lander:Magnus
Contributed to:
2015
2014
20132013
2018Wrote 6 papers:
- LCTES-2015-BairdGSWU #architecture #optimisation #pipes and filters
- Optimizing Transfers of Control in the Static Pipeline Architecture (RB, PG, MS, DBW, GRU), p. 10.
- LCTES-2015-BardizbanyanSWL #data access #performance #using
- Improving Data Access Efficiency by Using Context-Aware Loads and Stores (AB, MS, DBW, PLE), p. 10.
- DATE-2014-BardizbanyanSWL #data flow #dependence #detection #energy
- Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3) (AB, MS, DBW, PLE), pp. 1–4.
- CGO-2013-BardizbanyanGWSLMS #data access #performance #using
- Improving data access efficiency by using a tagless access buffer (TAB) (AB, PG, DBW, MS, PLE, SAM, PS), p. 11.
- LCTES-2013-FinlaysonDGUWST #performance #pipes and filters
- Improving processor efficiency by statically pipelining instructions (IF, BD, PG, GRU, DBW, MS, GST), pp. 33–44.
- PLDI-2018-TranJCKSK #co-evolution #design #named
- SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores (KAT, AJ, TEC, KK, MS, SK), pp. 328–343.