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Travelled to:
1 × Canada
1 × Ireland
1 × Mexico
5 × USA
Collaborated with:
D.B.Whalley P.A.Kulkarni S.R.Hines J.W.Davidson P.Gavin A.C.Cheng T.N.Mudge W.C.Kreahling S.Hines H.S.Lee M.Smelyanskiy C.J.Newburn Y.Peress V.Srinivasan E.S.Davidson M.J.Charney T.R.Puzak I.Finlayson B.Davis G.Uh M.Själander
Talks about:
instruct (7) optim (4) phase (3) order (3) fetch (3) processor (2) specif (2) search (2) stack (2) file (2)

Person: Gary S. Tyson

DBLP DBLP: Tyson:Gary_S=

Contributed to:

LCTES 20132013
LCTES 20092009
CGO 20072007
LCTES 20072007
CGO 20062006
LCTES 20062006
DAC 20042004
HPCA 20012001

Wrote 10 papers:

LCTES-2013-FinlaysonDGUWST #performance #pipes and filters
Improving processor efficiency by statically pipelining instructions (IF, BD, PG, GRU, DBW, MS, GST), pp. 33–44.
LCTES-2009-HinesPGWT #behaviour #lookahead
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE) (SRH, YP, PG, DBW, GST), pp. 119–128.
CGO-2007-KulkarniWT #algorithm #heuristic #optimisation #order
Evaluating Heuristic Optimization Phase Order Search Algorithms (PAK, DBW, GST), pp. 157–169.
LCTES-2007-HinesTW #using
Addressing instruction fetch bottlenecks by using an instruction register file (SRH, GST, DBW), pp. 165–174.
CGO-2006-KulkarniWTD #optimisation #order
Exhaustive Optimization Phase Order Space Exploration (PAK, DBW, GST, JWD), pp. 306–318.
LCTES-2006-KreahlingHWT #comparison #cost analysis #specification #using
Reducing the cost of conditional transfers of control by using comparison specifications (WCK, SH, DBW, GST), pp. 64–71.
LCTES-2006-KulkarniWTD #optimisation #order
In search of near-optimal optimization phase orderings (PAK, DBW, GST, JWD), pp. 83–92.
DAC-2004-ChengTM #embedded #named #synthesis
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors (ACC, GST, TNM), pp. 920–923.
HPCA-2001-LeeSNT #architecture #stack
Stack Value File: Custom Microarchitecture for the Stack (HHSL, MS, CJN, GST), pp. 5–14.
HPCA-2001-SrinivasanDTCP #branch
Branch History Guided Instruction Prefetching (VS, ESD, GST, MJC, TRP), pp. 291–300.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.