Travelled to:1 × China
1 × Ireland
2 × USA
Collaborated with:D.B.Whalley M.Själander G.Uh G.S.Tyson R.Baird S.R.Hines Y.Peress A.Bardizbanyan P.Larsson-Edefors S.A.McKee P.Stenström I.Finlayson B.Davis
Talks about:instruct (3) pipelin (2) static (2) improv (2) effici (2) access (2) fetch (2) architectur (1) processor (1) lookahead (1)
Person: Peter Gavin
DBLP: Gavin:Peter
Contributed to:
2015
201320132009Wrote 4 papers:
- LCTES-2015-BairdGSWU #architecture #optimisation #pipes and filters
- Optimizing Transfers of Control in the Static Pipeline Architecture (RB, PG, MS, DBW, GRU), p. 10.
- CGO-2013-BardizbanyanGWSLMS #data access #performance #using
- Improving data access efficiency by using a tagless access buffer (TAB) (AB, PG, DBW, MS, PLE, SAM, PS), p. 11.
- LCTES-2013-FinlaysonDGUWST #performance #pipes and filters
- Improving processor efficiency by statically pipelining instructions (IF, BD, PG, GRU, DBW, MS, GST), pp. 33–44.
- LCTES-2009-HinesPGWT #behaviour #lookahead
- Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE) (SRH, YP, PG, DBW, GST), pp. 119–128.