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Travelled to:
2 × Germany
Collaborated with:
R.Krishnan M.T.Bennebroek Y.Pu J.D.Echeverri J.P.d.Gyvez
Talks about:
interconnect (1) synthesi (1) frequenc (1) voltag (1) energi (1) effici (1) design (1) ultra (1) scale (1) power (1)

Person: Maurice Meijer

DBLP DBLP: Meijer:Maurice

Contributed to:

DATE 20142014
DATE Designers’ Forum 20062006

Wrote 2 papers:

DATE-2014-PuEMG #logic #power management #scalability #synthesis
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling (YP, JDE, MM, JPdG), pp. 1–2.
DATE-DF-2006-MeijerKB #design #energy
Energy-efficient FPGA interconnect design (MM, RK, MTB), pp. 42–47.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.