Travelled to:1 × USA
3 × France
3 × Germany
Collaborated with:A.Zjajo J.D.Echeverri J.R.Vázquez H.Fatemi H.R.Pourshaghaghi M.J.B.Asian S.Fabrie M.Vertregt Y.Pu M.Meijer B.Liu M.Ashouei J.Huisken A.Gomez C.Pinto A.Bartolini D.Rossi L.Benini
Talks about:standard (2) monitor (2) variat (2) signal (2) integr (2) design (2) analog (2) power (2) cell (2) low (2)
Person: José Pineda de Gyvez
DBLP: Gyvez:Jos=eacute=_Pineda_de
Contributed to:
20152014
20122012200820072004Wrote 8 papers:
- DATE-2015-GomezPBRBFG #design #energy #platform
- Reducing energy consumption in microcontroller-based platforms with low design margin co-processors (AG, CP, AB, DR, LB, HF, JPdG), pp. 269–272.
- DATE-2014-FabrieEVG #design #library #standard #variability
- Standard cell library tuning for variability tolerant designs (SF, JDE, MV, JPdG), pp. 1–6.
- DATE-2014-PuEMG #logic #power management #scalability #synthesis
- Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling (YP, JDE, MM, JPdG), pp. 1–2.
- DAC-2012-LiuAHG #standard
- Standard cell sizing for subthreshold operation (BL, MA, JH, JPdG), pp. 962–967.
- DATE-2012-PourshaghaghiFG
- Sliding-Mode Control to Compensate PVT Variations in dual core systems (HRP, HF, JPdG), pp. 1048–1053.
- DATE-2008-ZjajoG #analysis #fault #multi
- Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters (AZ, JPdG), pp. 74–79.
- DATE-2007-ZjajoAG #interactive #monitoring #parametricity #process
- Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.
- DATE-v2-2004-VazquezG #fault #monitoring #power management
- Power Supply Noise Monitor for Signal Integrity Faults (JRV, JPdG), pp. 1406–1407.