Travelled to:2 × USA
Collaborated with:X.Zhao S.K.Lim J.Burns G.Carpenter E.Kursun R.Puri J.D.Warnock
Talks about:technolog (1) processor (1) perspect (1) challeng (1) silicon (1) current (1) analysi (1) integr (1) impact (1) design (1)
Person: Michael Scheuermann
DBLP: Scheuermann:Michael
Contributed to:
20122011Wrote 2 papers:
- DAC-2012-ZhaoSL #3d #analysis
- Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs (XZ, MS, SKL), pp. 157–162.
- DAC-2011-BurnsCKPWS #3d #challenge #design
- Design, CAD and technology challenges for future processors: 3D perspectives (JB, GC, EK, RP, JDW, MS), p. 212.