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Open Knowledge
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Travelled to:
1 × United Kingdom
4 × Germany
6 × USA
Collaborated with:
M.T.Kandemir G.Chen S.W.Son W.Zhang Ö.Özturk G.Chen J.Dehmeshki M.V.Casique I.Kadayif S.P.Muralidhara D.R.Chakrabarti X.Tang Mahmut Taylan Kandemir Meenakshi Arunachalam C.M.Patrick A.N.Choudhary P.Unnikrishnan I.Kolcu
Talks about:
parallel (4) memori (4) cach (4) optim (3) level (3) loop (3) data (3) base (3) multiprocessor (2) prefetch (2)

Person: Mustafa Karaköy

DBLP DBLP: Karak=ouml=y:Mustafa

Contributed to:

HPDC 20102010
PPoPP 20092009
CGO 20072007
DATE 20062006
DATE 20052005
SAS 20052005
DAC 20032003
DATE 20032003
MLDM 20032003
SAS 20032003
DAC 20022002
PLDI 20192019

Wrote 13 papers:

HPDC-2010-KandemirMKS #multi
Computation mapping for multi-level storage cache hierarchies (MTK, SPM, MK, SWS), pp. 179–190.
Cashing in on hints for better prefetching and caching in PVFS and MPI-IO (CMP, MTK, MK, SWS, ANC), pp. 191–202.
PPoPP-2009-SonKKC #multi
A compiler-directed data prefetching scheme for chip multiprocessors (SWS, MTK, MK, DRC), pp. 209–218.
CGO-2007-OzturkCKK #latency #problem
Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems (ÖÖ, GC, MTK, MK), pp. 232–243.
DATE-2006-ChenOKK #array #data access #memory management
Dynamic scratch-pad memory management for irregular array access patterns (GC, ÖÖ, MTK, MK), pp. 931–936.
DATE-2005-ChenKK #approach #constraints #layout #memory management #network #optimisation
A Constraint Network Based Approach to Memory Layout Optimization (GC, MTK, MK), pp. 1156–1161.
SAS-2005-ChenKK #execution #memory management #reliability
Memory Space Conscious Loop Iteration Duplication for Reliable Execution (GC, MTK, MK), pp. 52–69.
DAC-2003-ZhangCKK #embedded #interprocedural #optimisation #performance
Interprocedural optimizations for improving data cache performance of array-intensive embedded applications (WZ, GC, MTK, MK), pp. 887–892.
DATE-2003-KandemirZK #parallel #runtime
Runtime Code Parallelization for On-Chip Multiprocessors (MTK, WZ, MK), pp. 10510–10515.
MLDM-2003-DehmeshkiKC #rule-based #set
A Rule-Based Scheme for Filtering Examples from Majority Class in an Imbalanced Training Set (JD, MK, MVC), pp. 215–223.
SAS-2003-UnnikrishnanCKKK #requirements
Loop Transformations for Reducing Data Space Requirements of Resource-Constrained Applications (PU, GC, MTK, MK, IK), pp. 383–400.
DAC-2002-KadayifKK #adaptation #energy #parallel
An energy saving strategy based on adaptive loop parallelization (IK, MTK, MK), pp. 195–200.
PLDI-2019-TangKKA #parallel
Co-optimizing memory-level parallelism and cache-level parallelism (XT, MTK, MK, MA), pp. 935–949.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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