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Travelled to:
1 × France
1 × Poland
2 × Germany
2 × United Kingdom
3 × USA
Collaborated with:
M.T.Kandemir M.Karaköy Ö.Özturk F.Li U.Sezer R.R.Brooks M.J.Irwin J.Ramanujam G.Chen
Talks about:
memori (4) base (4) approach (3) process (3) optim (3) code (3) constraint (2) schedul (2) network (2) address (2)

Person: Guilin Chen

DBLP DBLP: Chen:Guilin

Contributed to:

CGO 20072007
DAC 20062006
DATE 20062006
CC 20052005
CGO 20052005
DATE 20052005
SAS 20052005
DATE v1 20042004
CC 20032003

Wrote 11 papers:

CGO-2007-OzturkCKK #latency #problem
Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems (ÖÖ, GC, MTK, MK), pp. 232–243.
DAC-2006-OzturkCK #approach #constraints #network #optimisation #parallel
Optimizing code parallelization through a constraint network based approach (ÖÖ, GC, MTK), pp. 863–688.
DATE-2006-ChenOKK #array #data access #memory management
Dynamic scratch-pad memory management for irregular array access patterns (GC, ÖÖ, MTK, MK), pp. 931–936.
CC-2005-LiCKB #approach #security
A Compiler-Based Approach to Data Security (FL, GC, MTK, RRB), pp. 188–203.
CGO-2005-ChenK #code generation #optimisation
Optimizing Address Code Generation for Array-Intensive DSP Applications (GC, MTK), pp. 141–152.
DATE-2005-ChenKK #approach #constraints #layout #memory management #network #optimisation
A Constraint Network Based Approach to Memory Layout Optimization (GC, MTK, MK), pp. 1156–1161.
DATE-2005-KandemirC #embedded #process #scheduling
Locality-Aware Process Scheduling for Embedded MPSoCs (MTK, GC), pp. 870–875.
DATE-2005-KandemirLCCO #embedded #in memory #trade-off
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing (MTK, FL, GC, GC, ÖÖ), pp. 1026–1031.
SAS-2005-ChenKK #execution #memory management #reliability
Memory Space Conscious Loop Iteration Duplication for Reliable Execution (GC, MTK, MK), pp. 52–69.
DATE-v1-2004-ChenKS #process #scheduling
Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms (GC, MTK, US), pp. 486–493.
Address Register Assignment for Reducing Code Size (MTK, MJI, GC, JR), pp. 273–289.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.