Travelled to:1 × India
1 × USA
Collaborated with:S.Mitra T.Karnik M.Zhang A.Biswas C.Recchia S.S.Mukherjee V.Ambrose L.Chan A.Jaleel A.E.Papathanasiou M.Plaster
Talks about:technolog (1) challeng (1) explain (1) anomali (1) measur (1) design (1) logic (1) error (1) soft (1) cach (1)
Person: Norbert Seifert
DBLP: Seifert:Norbert
Contributed to:
2010
2005Wrote 2 papers:
- HPCA-2010-BiswasRMACJPPS #metric #using
- Explaining cache SER anomaly using DUE AVF measurement (AB, CR, SSM, VA, LC, AJ, AEP, MP, NS), pp. 1–12.
- DAC-2005-MitraKSZ #challenge #design #fault #logic
- Logic soft errors in sub-65nm technologies design and CAD challenges (SM, TK, NS, MZ), pp. 2–4.