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Travelled to:
1 × India
1 × United Kingdom
5 × USA
Collaborated with:
B.L.Jacob S.C.S.Jr. J.S.Emer M.Mattina B.Ganesh D.Wang J.Nuzman A.Moga H.H.Najaf-abadi S.Subramaniam W.Heirman T.E.Carlson K.V.Craeynest I.Hur L.Eeckhout S.H.Pugsley Z.Chishti C.Wilkerson P.Chuang R.L.Scott S.Lu K.Chow R.Balasubramonian A.Biswas C.Recchia S.S.Mukherjee V.Ambrose L.Chan A.E.Papathanasiou M.Plaster N.Seifert
Talks about:
cach (6) workload (3) architectur (2) prefetch (2) perform (2) memori (2) use (2) undersubscrib (1) bioinformat (1) understand (1)

Person: Aamer Jaleel

DBLP DBLP: Jaleel:Aamer

Contributed to:

HPCA 20152015
HPCA 20142014
ASPLOS 20122012
HPCA 20102010
HPCA 20072007
HPCA 20062006
HPCA 20052005

Wrote 8 papers:

HPCA-2015-JaleelNMSE #latency
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches (AJ, JN, AM, SCSJ, JSE), pp. 343–353.
HPCA-2014-HeirmanCCHJE #architecture #clustering #thread
Undersubscribed threading on clustered cache architectures (WH, TEC, KVC, IH, AJ, LE), pp. 678–689.
HPCA-2014-PugsleyCWCSJLCB #evaluation #runtime
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers (SHP, ZC, CW, PfC, RLS, AJ, SLL, KC, RB), pp. 626–637.
ASPLOS-2012-JaleelNSSE #named #scheduling
CRUISE: cache replacement and utility-aware scheduling (AJ, HHNa, SS, SCSJ, JSE), pp. 249–260.
HPCA-2010-BiswasRMACJPPS #metric #using
Explaining cache SER anomaly using DUE AVF measurement (AB, CR, SSM, VA, LC, AJ, AEP, MP, NS), pp. 1–12.
HPCA-2007-GaneshJWJ #architecture #comprehension #memory management #scalability
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling (BG, AJ, DW, BLJ), pp. 109–120.
HPCA-2006-JaleelMJ #case study #data mining #mining #parallel #performance
Last level cache (LLC) performance of data mining workloads on a CMP — a case study of parallel bioinformatics workloads (AJ, MM, BLJ), pp. 88–98.
HPCA-2005-JaleelJ #memory management #using
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions (AJ, BLJ), pp. 191–200.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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