BibSLEIGH — Subhasish

Travelled to:

4 × France
4 × Germany
8 × USA

Collaborated with:

J.Zhang N.Patil H.P.Wong C.Cher D.Lin S.Park H.Wei S.A.Seshia H.Cho M.M.Shulaker A.Lin ∅ E.H.Volkerink Y.Li S.Mirkhani G.Hills T.Hong F.Fallah N.Hakim N.Nicolici Y.Kanoria A.Montanari K.Brelsford P.N.Sanda S.Makar W.Li E.Singh C.W.Barrett H.Chen K.A.Campbell D.Chen T.Shepherd J.Abraham V.Chandra S.M.Mueller A.Bracy H.Wang A.Hazeghi D.Gizopoulos K.Roy P.Sanda J.Deng T.Karnik N.Seifert M.Zhang E.S S.Kumar E.Rentschler J.A.Abraham L.Leem J.Bau Q.A.Jacobson T.F.Wu M.M.Sabry C.Mackin J.V.Rethy G.G.E.Gielen D.S.Gardner S.Bobba G.D.Micheli E.Mintarno J.Skaf R.Zheng J.Velamala Y.Cao S.P.Boyd R.W.Dutton C.Lee L.Liyanage C.Chen W.S.Lee R.Parsa S.Chong J.Provine J.Watt R.T.Howe

Talks about:

nanotub (11) carbon (11) error (11) circuit (8) silicon (7) design (7) post (7) use (7) challeng (6) valid (6)

Person: Subhasish Mitra

DBLP: Mitra:Subhasish

Contributed to:

2015

2014

2013

2012

2010

2009

2008

2007

2005

2017

Wrote 34 papers:

DAC-2015-CampbellLMC #debugging #detection #fault #hybrid #synthesis #using #validation: Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles (KAC, DL, SM, DC), p. 6.
DAC-2015-ChoCSM #component #comprehension #fault: Understanding soft errors in uncore components (HC, CYC, TS, SM), p. 6.
DATE-2015-LinSKRM #debugging #detection #effectiveness #fault #performance #testing #validation: Quick error detection tests with fast runtimes for effective post-silicon validation and debug (DL, ES, SK, ER, SM), pp. 1168–1173.
DATE-2015-MirkhaniMCA #design #estimation #fault #performance: Efficient soft error vulnerability estimation of complex designs (SM, SM, CYC, JA), pp. 103–108.
DATE-2015-ShulakerWSWWM #3d #concept #integration: Monolithic 3D integration: a path from concept to reality (MMS, TFW, MMS, HW, HSPW, SM), pp. 1197–1202.
DATE-2014-ChandraMCCM: Cross layer resiliency in real world (VC, SM, CYC, SMM), p. 1.
DAC-2013-ChoMCAM #design #evaluation #fault #injection #robust: Quantitative evaluation of soft error injection techniques for robust system design (HC, SM, CYC, JAA, SM), p. 10.
DAC-2013-HillsZMSWWM #agile #design #guidelines: Rapid exploration of processing and design guidelines to overcome carbon nanotube variations (GH, JZ, CM, MMS, HW, HSPW, SM), p. 10.
DAC-2013-ShulakerRHCGWM #named: Sacha: the Stanford carbon nanotube controlled handshaking robot (MMS, JVR, GH, HYC, GGEG, HSPW, SM), p. 3.
DATE-2013-LinHLFGHM #challenge #detection #fault #validation: Overcoming post-silicon validation challenges through quick error detection (QED) (DL, TH, YL, FF, DSG, NH, SM), pp. 320–325.
DATE-2013-WeiSHCLLZWM #challenge: Carbon nanotube circuits: opportunities and challenges (HW, MMS, GH, HYC, CSL, LL, JZ, HSPW, SM), pp. 619–624.
DAC-2012-LinHFHM #debugging #detection #effectiveness #validation: Quick detection of difficult bugs for effective post-silicon validation (DL, TH, FF, NH, SM), pp. 561–566.
DATE-2012-ChenLPCPWHWM #design: Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique (CC, WSL, RP, SC, JP, JW, RTH, HSPW, SM), pp. 1361–1366.
DAC-2010-MitraSN #challenge #validation: Post-silicon validation opportunities, challenges and recent advances (SM, SAS, NN), pp. 12–17.
DAC-2010-ParkBWM #debugging #graph #locality #named #using: BLoG: post-silicon bug localization in processors using bug localization graphs (SBP, AB, HW, SM), pp. 368–373.
DAC-2010-ZhangBPLWMM #correlation: Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement (JZ, SB, NP, AL, HSPW, GDM, SM), pp. 889–892.
DATE-2010-KanoriaMM #analysis #markov #monte carlo #statistics #using: Statistical static timing analysis using Markov chain Monte Carlo (YK, SM, AM), pp. 813–818.
DATE-2010-LeemCBJM #architecture #fault #named #probability: ERSA: Error Resilient System Architecture for probabilistic applications (LL, HC, JB, QAJ, SM), pp. 1560–1565.
DATE-2010-MintarnoSZVCBDM #self: Optimized self-tuning for circuit aging (EM, JS, RZ, JV, YC, SPB, RWD, SM), pp. 586–591.
DATE-2010-MitraBS #challenge #metric #optimisation: Cross-layer resilience challenges: Metrics and optimization (SM, KB, PNS), pp. 1029–1034.
DATE-2010-ZhangPLWM: Carbon nanotube circuits: Living with imperfections and variations (JZ, NP, AL, HSPW, SM), pp. 1159–1164.
DAC-2009-PatilLZWM #logic #using: Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions (NP, AL, JZ, HSPW, SM), pp. 304–309.
DAC-2009-ZhangPHM: Carbon nanotube circuits in the presence of carbon nanotube density variations (JZ, NP, AH, SM), pp. 71–76.
DATE-2009-MitraZPW #logic #using: Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (SM, JZ, NP, HW), pp. 436–441.
DAC-2008-ParkM #analysis #debugging #locality #named: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors (SBP, SM), pp. 373–378.
DATE-2008-GizopoulosRMS #case study #fault: Soft Errors: System Effects, Protection Techniques and Case Studies (DG, KR, SM, PS).
DATE-2008-LiMM #concurrent #named #self #using: CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns (YL, SM, SM), pp. 885–890.
DATE-2008-Mitra #challenge #reliability #robust: Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges (SM), pp. 941–946.
DATE-2008-ZhangPM #design #guidelines #logic: Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits (JZ, NP, SM), pp. 1009–1014.
DAC-2007-PatilDWM #automation #design: Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits (NP, JD, HSPW, SM), pp. 958–961.
DATE-2007-SeshiaLM #fault: Verification-guided soft error resilience (SAS, WL, SM), pp. 1442–1447.
DAC-2005-MitraKSZ #challenge #design #fault #logic: Logic soft errors in sub-65nm technologies design and CAD challenges (SM, TK, NS, MZ), pp. 2–4.
DAC-2005-VolkerinkM #architecture #using: Response compaction with any number of unknowns using a new LFSR architecture (EHV, SM), pp. 117–122.
CAV-2017-SinghBM #debugging #detection #fault #formal method #locality #named #validation: E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods (ES, CWB, SM), pp. 104–125.