BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × Spain
3 × USA
Collaborated with:
K.I.Farkas N.P.Jouppi M.A.R.Saghir C.G.Lee T.M.Aamodt P.Hammarlund H.Wang J.P.Shen
Talks about:
processor (3) prescient (1) prefetch (1) instruct (1) consider (1) support (1) schedul (1) multipl (1) hardwar (1) exploit (1)

Person: Paul Chow

DBLP DBLP: Chow:Paul

Contributed to:

HPCA 20042004
ASPLOS 19961996
HPCA 19961996
HPCA 19951995

Wrote 4 papers:

HPCA-2004-AamodtCHWS #hardware
Hardware Support for Prescient Instruction Prefetch (TMA, PC, PH, HW, JPS), pp. 84–95.
Exploiting Dual Data-Memory Banks in Digital Signal Processors (MARS, PC, CGL), pp. 234–243.
HPCA-1996-FarkasJC #design
Register File Design Considerations in Dynamically Scheduled Processors (KIF, NPJ, PC), pp. 40–51.
HPCA-1995-FarkasJC #execution #how #multi #question
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? (KIF, NPJ, PC), pp. 78–89.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.