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Travelled to:
1 × France
2 × Germany
Collaborated with:
C.Roma ∅ D.Iezzi D.Rimondi S.Santapa
Talks about:
qualifi (2) signal (2) memori (2) design (2) fulli (2) flow (2) mix (2) technolog (1) hierarchi (1) volatil (1)

Person: Pierluigi Daglio

DBLP DBLP: Daglio:Pierluigi

Contributed to:

DATE Designers’ Forum 20062006
DATE DF 20042004
DATE 20032003

Wrote 3 papers:

DATE-DF-2006-Daglio #design #embedded #verification
A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories (PD), pp. 94–99.
DATE-DF-2004-DaglioIRRS #component #performance #simulation
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.
DATE-2003-DaglioR #bottom-up #design #top-down
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies (PD, CR), pp. 20274–20279.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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