1 × Germany
1 × USA
G.Baeckler S.Safarpour A.G.Veneris M.Hutton J.Schleicher S.Cheung K.K.Chua H.K.Phoo
fpga (2) methodolog (1) technolog (1) synthesi (1) structur (1) boolean (1) effici (1) verif (1) match (1) base (1)
Person: Richard Yuan
Wrote 2 papers:
- DAC-2006-SafarpourVBY #performance #satisfiability
- Efficient SAT-based Boolean matching for FPGA technology mapping (SS, AGV, GB, RY), pp. 466–471.
- DATE-DF-2006-HuttonYSBCCP #synthesis #verification
- A methodology for FPGA to structured-ASIC synthesis and verification (MH, RY, JS, GB, SC, KKC, HKP), pp. 64–69.