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Travelled to:
1 × Germany
2 × USA
3 × France
Collaborated with:
A.G.Veneris R.Drechsler B.Keng G.Baeckler R.Yuan G.Fey J.Lee H.Mangassarian F.N.Najm M.S.Abadir
Talks about:
boolean (3) base (3) satisfi (2) debug (2) autom (2) sat (2) technolog (1) techniqu (1) sherlock (1) diagnosi (1)

Person: Sean Safarpour

DBLP DBLP: Safarpour:Sean

Contributed to:

DATE 20112011
DAC 20092009
DATE 20072007
DAC 20062006
DATE 20062006
DATE v1 20042004

Wrote 7 papers:

DATE-2011-KengSV #automation #debugging
Automated debugging of SystemVerilog assertions (BK, SS, AGV), pp. 323–328.
DAC-2009-VenerisS
The day Sherlock Holmes decided to do EDA (AGV, SS), pp. 631–634.
DATE-2007-MangassarianVSNA #estimation #process #pseudo #satisfiability #using
Maximum circuit activity estimation using pseudo-boolean satisfiability (HM, AGV, SS, FNN, MSA), pp. 1538–1543.
DATE-2007-SafarpourV #abstraction #automation #debugging #design #refinement
Abstraction and refinement techniques in automated design debugging (SS, AGV), pp. 1182–1187.
DAC-2006-SafarpourVBY #performance #satisfiability
Efficient SAT-based Boolean matching for FPGA technology mapping (SS, AGV, GB, RY), pp. 466–471.
DATE-2006-FeySVD #on the #satisfiability
On the relation between simulation-based and SAT-based diagnosis (GF, SS, AGV, RD), pp. 1139–1144.
DATE-v1-2004-SafarpourVDL #satisfiability
Managing Don’t Cares in Boolean Satisfiability (SS, AGV, RD, JL), pp. 260–265.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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