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Travelled to:
1 × France
1 × Italy
1 × USA
Collaborated with:
G.Araujo G.Marcilio L.C.V.d.Santos B.Albertini P.Viana E.Barros R.Azevedo G.Ottoni S.Rajagopalan S.Malik
Talks about:
methodolog (1) hierarchi (1) techniqu (1) platform (1) behavior (1) program (1) address (1) regist (1) memori (1) design (1)

Person: Sandro Rigo

DBLP DBLP: Rigo:Sandro

Contributed to:

DAC 20092009
DATE v1 20042004
CC 20012001

Wrote 3 papers:

DAC-2009-MarcilioSAR #behaviour #novel #verification
A novel verification technique to uncover out-of-order DUV behaviors (GM, LCVdS, BA, SR), pp. 448–453.
DATE-v1-2004-VianaBRAA #design #memory management #modelling #simulation
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology (PV, EB, SR, RA, GA), pp. 734–735.
CC-2001-OttoniRARM #embedded #source code
Optimal Live Range Merge for Address Register Allocation in Embedded Programs (GO, SR, GA, SR, SM), pp. 274–288.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.