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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
G.Araujo C.Hoffman L.Ramos E.W.Netto P.Centoducatte P.Viana E.Barros S.Rigo
Talks about:
memori (2) base (2) methodolog (1) hierarchi (1) techniqu (1) platform (1) compress (1) correct (1) analysi (1) profil (1)

Person: Rodolfo Azevedo

DBLP DBLP: Azevedo:Rodolfo

Contributed to:

DATE 20142014
DAC 20042004
DATE v1 20042004

Wrote 3 papers:

DATE-2014-HoffmanRAA #analysis #fault #memory management
Wear-out analysis of Error Correction Techniques in Phase-Change Memory (CH, LR, RA, GA), pp. 1–4.
DAC-2004-NettoACA #multi
Multi-profile based code compression (EWN, RA, PC, GA), pp. 244–249.
DATE-v1-2004-VianaBRAA #design #memory management #modelling #simulation
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology (PV, EB, SR, RA, GA), pp. 734–735.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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