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Travelled to:
1 × Austria
1 × USA
2 × France
Collaborated with:
P.Viana A.Gordon-Ross F.Vahid L.Silva A.Sampaio W.A.Najjar E.J.Keogh S.Rigo R.Azevedo G.Araujo
Talks about:
cach (3) configur (2) methodolog (1) hierarchi (1) strategi (1) platform (1) softwar (1) perform (1) hardwar (1) subset (1)

Person: Edna Barros

DBLP DBLP: Barros:Edna

Contributed to:

DATE 20072007
DAC 20062006
DATE v1 20042004
FME 19971997

Wrote 4 papers:

DATE-2007-Gordon-RossVVNB #configuration management #energy #performance
A one-shot configurable-cache tuner for improved energy and performance (AGR, PV, FV, WAN, EB), pp. 755–760.
DAC-2006-VianaGKBV #configuration management #performance
Configurable cache subsetting for fast cache tuning (PV, AGR, EJK, EB, FV), pp. 695–700.
DATE-v1-2004-VianaBRAA #design #memory management #modelling #simulation
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology (PV, EB, SR, RA, GA), pp. 734–735.
FME-1997-SilvaSB #clustering #hardware #normalisation #reduction
A Normal Form Reduction Strategy for Hardware/Software Partitioning (LS, AS, EB), pp. 624–643.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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