Travelled to:1 × Canada
1 × France
1 × Germany
1 × Italy
4 × USA
Collaborated with:R.Azevedo E.Borin S.Malik M.S.Cintra S.Rigo A.Baldassin M.T.Lee C.Hoffman L.Ramos C.Wang Y.Wu E.W.Netto P.Centoducatte P.Viana E.Barros G.Ottoni S.Rajagopalan
Talks about:memori (5) regist (3) alloc (3) base (3) error (2) rang (2) live (2) code (2) use (2) architectur (1)
Person: Guido Araujo
DBLP: Araujo:Guido
Contributed to:
2015
2014
2006
20042004
2001
20001996Wrote 8 papers:
- PPoPP-2015-BaldassinBA #memory management #performance #transaction
- Performance implications of dynamic memory allocators on transactional memory systems (AB, EB, GA), pp. 87–96.
- DATE-2014-HoffmanRAA #analysis #fault #memory management
- Wear-out analysis of Error Correction Techniques in Phase-Change Memory (CH, LR, RA, GA), pp. 1–4.
- CGO-2006-BorinWWA #control flow #detection #fault
- Software-Based Transparent and Comprehensive Control-Flow Error Detection (EB, CW, YW, GA), pp. 333–345.
- DAC-2004-NettoACA #multi
- Multi-profile based code compression (EWN, RA, PC, GA), pp. 244–249.
- DATE-v1-2004-VianaBRAA #design #memory management #modelling #simulation
- Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology (PV, EB, SR, RA, GA), pp. 734–735.
- CC-2001-OttoniRARM #embedded #source code
- Optimal Live Range Merge for Address Register Allocation in Embedded Programs (GO, SR, GA, SR, SM), pp. 274–288.
- LCTES-2000-CintraA #array #using
- Array Reference Allocation Using SSA-Form and Live Range Growth (MSC, GA), pp. 48–62.
- DAC-1996-AraujoML #architecture #code generation #using
- Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures (GA, SM, MTCL), pp. 591–596.