Travelled to:1 × France
2 × USA
Collaborated with:S.S.Sapatnekar S.Hu C.J.Alpert J.Hu Z.Li W.Shi C.C.N.Sze
Talks about:fast (2) comparison (1) technolog (1) implement (1) constrain (1) algorithm (1) incorpor (1) parasit (1) minimum (1) circuit (1)
Person: Shrirang K. Karandikar
DBLP: Karandikar:Shrirang_K=
Contributed to:
2006
20042001Wrote 3 papers:
- DAC-2006-HuAHKLSS #algorithm #performance
- Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
- DATE-v2-2004-KarandikarS #implementation #performance
- Fast Comparisons of Circuit Implementations (SKK, SSS), pp. 910–915.
- DAC-2001-KarandikarS #logic
- Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect (SKK, SSS), pp. 377–382.