Travelled to:1 × France
5 × USA
Collaborated with:J.Hu Z.Li C.J.Alpert W.Shi M.Ketkar Z.Jiang C.C.N.Sze X.Zhao Y.Guo Z.Feng Q.Li P.Li Y.Wei S.S.Sapatnekar Y.Liu J.Wu Y.Shi Y.Jin Y.Hu X.Li S.K.Karandikar
Talks about:design (3) time (3) minimum (2) buffer (2) cost (2) net (2) cyberattack (1) differenti (1) construct (1) constrain (1)
Person: Shiyan Hu
DBLP: Hu:Shiyan
Contributed to:
2015
20132010200920072006Wrote 8 papers:
- DAC-2015-LiuHWSJHL #assessment #detection #smarttech
- Impact assessment of net metering on smart home cyberattack detection (YL, SH, JW, YS, YJ, YH, XL), p. 6.
- DATE-2013-WeiLSHAS #design #effectiveness #named
- CATALYST: planning layer directives for effective design closure (YW, ZL, CCNS, SH, CJA, SSS), pp. 1873–1878.
- DAC-2010-ZhaoGFH #optimisation #parallel
- Parallel hierarchical cross entropy optimization for on-chip decap budgeting (XZ, YG, ZF, SH), pp. 843–848.
- DAC-2009-HuLA #approximate #polynomial
- A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion (SH, ZL, CJA), pp. 424–429.
- DAC-2007-HuKH #design
- Gate Sizing For Cell Library-Based Designs (SH, MK, JH), pp. 847–852.
- DAC-2007-JiangHS #design #difference
- A New Twisted Differential Line Structure in Global Bus Design (ZJ, SH, WS), pp. 180–183.
- DAC-2006-HuAHKLSS #algorithm #performance
- Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
- DAC-2006-HuLHL #network
- Steiner network construction for timing critical nets (SH, QL, JH, PL), pp. 379–384.